drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h- Extension
.h- Size
- 1655 bytes
- Lines
- 50
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hpd_regs.h
Detected Declarations
struct hw_hpd
Annotated Snippet
struct hw_hpd {
struct hw_gpio base;
const struct hpd_registers *regs;
const struct hpd_sh_mask *shifts;
const struct hpd_sh_mask *masks;
};
#define HW_HPD_FROM_BASE(hw_gpio) \
container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base)
void dal_hw_hpd_init(
struct hw_hpd **hw_hpd,
struct dc_context *ctx,
enum gpio_id id,
uint32_t en);
struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio);
#endif
Annotation
- Immediate include surface: `hpd_regs.h`.
- Detected declarations: `struct hw_hpd`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.