drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
Extension
.c
Size
9066 bytes
Lines
287
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "core_types.h"
#include "dc_bios_types.h"
#include "dcn30_hpo_frl_link_encoder.h"
#include "reg_helper.h"
#include "dcn10/dcn10_link_encoder.h"

#define DC_LOGGER enc3->base.ctx->logger

#define REG(reg) (enc3->regs->reg)

#undef FN
#define FN(reg_name, field_name) enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name

#define CTX enc3->base.ctx

void hpo_frl_link_enc3_setup_link_encoder(struct hpo_frl_link_encoder *enc,
						 int lane_count)
{
	struct dcn30_hpo_frl_link_encoder *enc3 = DCN30_HPO_FRL_LINK_ENC_FROM_HPO_FRL_LINK_ENC(enc);

	DC_LOG_DEBUG("Entering [%s]\n", __func__);

	if (enc->ctx->dc->caps.ips_v2_support) {
		REG_UPDATE(HDMI_FRL_ENC_MEM_CTRL,
			METERBUFFER_MEM_PWR_DIS, 1);
		REG_WAIT(HDMI_FRL_ENC_MEM_CTRL,	METERBUFFER_MEM_PWR_STATE, 0, 1, 100);
	}
	/* Enable Link encoder clock */
	REG_UPDATE(HDMI_LINK_ENC_CLK_CTRL,
		   HDMI_LINK_ENC_CLOCK_EN, 1);

	/* Configure lane count of FRL encoder */
	REG_UPDATE(HDMI_FRL_ENC_CONFIG,
		   HDMI_LINK_LANE_COUNT, lane_count == 3 ? 0 : 1);

	/* Reset link encoder */
	REG_UPDATE_2(HDMI_LINK_ENC_CONTROL,
		     HDMI_LINK_ENC_ENABLE, 0,
		     HDMI_LINK_ENC_SOFT_RESET, 1);

	REG_UPDATE(HDMI_LINK_ENC_CONTROL,
		   HDMI_LINK_ENC_SOFT_RESET, 0);

	/* Enable link encoder */
	REG_UPDATE(HDMI_LINK_ENC_CONTROL,
		   HDMI_LINK_ENC_ENABLE, 1);

	DC_LOG_HDMI_FRL("Exiting [%s]\n", __func__);
}

void hpo_frl_link_enc3_set_training_pattern(struct hpo_frl_link_encoder *enc,
						   uint32_t lane0_pattern,
						   uint32_t lane1_pattern,
						   uint32_t lane2_pattern,
						   uint32_t lane3_pattern)
{
	struct dcn30_hpo_frl_link_encoder *enc3 = DCN30_HPO_FRL_LINK_ENC_FROM_HPO_FRL_LINK_ENC(enc);

	/* Configure lane count of FRL encoder */
	REG_UPDATE(HDMI_FRL_ENC_CONFIG,
		   HDMI_LINK_TRAINING_ENABLE, 1);

	if (lane0_pattern < 8)
		REG_UPDATE(HDMI_FRL_ENC_CONFIG,
			   HDMI_LINK_LANE0_TRAINING_PATTERN, lane0_pattern);

	if (lane1_pattern < 8)
		REG_UPDATE(HDMI_FRL_ENC_CONFIG,
			   HDMI_LINK_LANE1_TRAINING_PATTERN, lane1_pattern);

	if (lane2_pattern < 8)
		REG_UPDATE(HDMI_FRL_ENC_CONFIG,
			   HDMI_LINK_LANE2_TRAINING_PATTERN, lane2_pattern);

	if (lane3_pattern < 8)
		REG_UPDATE(HDMI_FRL_ENC_CONFIG,
			   HDMI_LINK_LANE3_TRAINING_PATTERN, lane3_pattern);
}

void hpo_frl_link_enc3_get_training_pattern(struct hpo_frl_link_encoder *enc,
						   uint32_t *lane0_pattern,
						   uint32_t *lane1_pattern,
						   uint32_t *lane2_pattern,
						   uint32_t *lane3_pattern)
{
	struct dcn30_hpo_frl_link_encoder *enc3 = DCN30_HPO_FRL_LINK_ENC_FROM_HPO_FRL_LINK_ENC(enc);

	/* Configure lane count of FRL encoder */
	REG_GET_4(HDMI_FRL_ENC_CONFIG,
		  HDMI_LINK_LANE0_TRAINING_PATTERN, lane0_pattern,

Annotation

Implementation Notes