drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.h
Extension
.h
Size
5894 bytes
Lines
147
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn30_hpo_frl_link_encoder_registers {
	uint32_t HDMI_LINK_ENC_CLK_CTRL;
	uint32_t HDMI_LINK_ENC_CONTROL;
	uint32_t HDMI_FRL_ENC_CONFIG;
	uint32_t HDMI_FRL_ENC_CONFIG2;
	uint32_t HDMI_FRL_ENC_MEM_CTRL;
};

#define DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(mask_sh)\
	SE_SF(HDMI_LINK_ENC_CLK_CTRL, HDMI_LINK_ENC_CLOCK_EN, mask_sh),\
	SE_SF(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_ENABLE, mask_sh),\
	SE_SF(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_SOFT_RESET, mask_sh),\
	SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_DIS, mask_sh),\
	SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_FORCE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_STATE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE_COUNT, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_TRAINING_ENABLE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE0_TRAINING_PATTERN, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE1_TRAINING_PATTERN, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE2_TRAINING_PATTERN, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE3_TRAINING_PATTERN, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_MAX_JITTER_VALUE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_THRESHOLD, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_CAL_EN, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_RC_COMPRESS_DISABLE, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_FRL_HDMISTREAMCLK_DB_SEL, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_MAX_JITTER_VALUE_RESET, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_EXCEED_STATUS, mask_sh),\
	SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS, mask_sh)

#define HPO_FRL_LINK_ENC_DCN3_REG_FIELD_LIST(type) \
	type HDMI_LINK_ENC_CLOCK_EN;\
	type HDMI_LINK_ENC_ENABLE;\
	type HDMI_LINK_ENC_SOFT_RESET;\
	type HDMI_LINK_LANE_COUNT;\
	type HDMI_LINK_TRAINING_ENABLE;\
	type HDMI_LINK_LANE0_TRAINING_PATTERN;\
	type HDMI_LINK_LANE1_TRAINING_PATTERN;\
	type HDMI_LINK_LANE2_TRAINING_PATTERN;\
	type HDMI_LINK_LANE3_TRAINING_PATTERN;\
	type HDMI_LINK_MAX_JITTER_VALUE;\
	type HDMI_LINK_JITTER_THRESHOLD;\
	type HDMI_LINK_JITTER_CAL_EN;\
	type HDMI_LINK_RC_COMPRESS_DISABLE;\
	type METERBUFFER_MEM_PWR_DIS;\
	type METERBUFFER_MEM_PWR_STATE;\
	type METERBUFFER_MEM_PWR_FORCE;\
	type METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE;\
	type HDMI_FRL_HDMISTREAMCLK_DB_SEL;\
	type HDMI_LINK_MAX_JITTER_VALUE_RESET;\
	type HDMI_LINK_JITTER_EXCEED_STATUS;\
	type HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS


struct dcn30_hpo_frl_link_encoder_shift {
	HPO_FRL_LINK_ENC_DCN3_REG_FIELD_LIST(uint8_t);
};

struct dcn30_hpo_frl_link_encoder_mask {
	HPO_FRL_LINK_ENC_DCN3_REG_FIELD_LIST(uint32_t);
};

struct dcn30_hpo_frl_link_encoder {
	struct hpo_frl_link_encoder base;
	const struct dcn30_hpo_frl_link_encoder_registers *regs;
	const struct dcn30_hpo_frl_link_encoder_shift *hpo_le_shift;
	const struct dcn30_hpo_frl_link_encoder_mask *hpo_le_mask;
};

void hpo_frl_link_enc3_setup_link_encoder(struct hpo_frl_link_encoder *enc,
						 int lane_count);

void hpo_frl_link_enc3_set_training_pattern(struct hpo_frl_link_encoder *enc,
						uint32_t lane0_pattern,
						uint32_t lane1_pattern,
						uint32_t lane2_pattern,
						uint32_t lane3_pattern);

void hpo_frl_link_enc3_get_training_pattern(struct hpo_frl_link_encoder *enc,
						uint32_t *lane0_pattern,
						uint32_t *lane1_pattern,
						uint32_t *lane2_pattern,
						uint32_t *lane3_pattern);

void hpo_frl_link_enc3_enable_output(struct hpo_frl_link_encoder *enc);

void hpo_frl_link_enc3_disable(struct hpo_frl_link_encoder *enc);

void hpo_frl_link_enc3_read_state(struct hpo_frl_link_encoder *enc,

Annotation

Implementation Notes