drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
Extension
.c
Size
33467 bytes
Lines
1044
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				     HDMI_DEEP_COLOR_DEPTH, 1,
				     HDMI_DEEP_COLOR_ENABLE, 0);
		} else {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				     HDMI_DEEP_COLOR_DEPTH, 1,
				     HDMI_DEEP_COLOR_ENABLE, 1);
		}
		break;
	case COLOR_DEPTH_121212:
		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				     HDMI_DEEP_COLOR_DEPTH, 2,
				     HDMI_DEEP_COLOR_ENABLE, 0);
		} else {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				     HDMI_DEEP_COLOR_DEPTH, 2,
				     HDMI_DEEP_COLOR_ENABLE, 1);
		}
		break;
	default:
		break;
	}

	/* When compression active, CD/PP/Phase field shall be zero in GCP */
	if (crtc_timing->flags.DSC) {
		REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				HDMI_DEEP_COLOR_DEPTH, 0,
				HDMI_DEEP_COLOR_ENABLE, 0);
	} else {
		REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
			HDMI_DSC_MODE, 0);
	}

	/* Configure ODM combine mode */
	switch (odm_combine_num_segments) {
	case 1:
		REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
			   FIFO_ODM_COMBINE_MODE, 0);

		if (enc3->hpo_se_mask->HDMI_ODM_COMBINE_MODE)
			REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
				   HDMI_ODM_COMBINE_MODE, 0);
		break;
	case 2:
		REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
			   FIFO_ODM_COMBINE_MODE, 1);

		if (enc3->hpo_se_mask->HDMI_ODM_COMBINE_MODE)
			REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
				   HDMI_ODM_COMBINE_MODE, 1);
		break;
	case 4:
		REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
			   FIFO_ODM_COMBINE_MODE, 3);
		break;
	default:
		break;
	}

	/* Configure horizontal active and blank size */
	h_active = crtc_timing->h_addressable + crtc_timing->h_border_left + crtc_timing->h_border_right;
	h_blank = crtc_timing->h_total - h_active;

	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ||
	    crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
		h_active /= 2;
		h_blank /= 2;
	}


	REG_SET_2(HDMI_TB_ENC_H_ACTIVE_BLANK, 0,
		  HDMI_H_ACTIVE, h_active,
		  HDMI_H_BLANK, h_blank);

	/* Configure borrow parameters */
	REG_UPDATE(HDMI_TB_ENC_MODE,
		   HDMI_BORROW_MODE, borrow_params->borrow_mode);

	REG_UPDATE(HDMI_TB_ENC_PACKET_CONTROL,
		   HDMI_MAX_PACKETS_PER_LINE, borrow_params->audio_packets_line);

	REG_SET_2(HDMI_TB_ENC_HC_ACTIVE_BLANK, 0,
		  HDMI_HC_ACTIVE, borrow_params->hc_active_target,
		  HDMI_HC_BLANK, borrow_params->hc_blank_target);

	/* Enable transmission of General Control packet on every frame */
	REG_UPDATE_2(HDMI_TB_ENC_VBI_PACKET_CONTROL1,
		     HDMI_GC_CONT, 1,

Annotation

Implementation Notes