drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c- Extension
.c- Size
- 25918 bytes
- Lines
- 786
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dc_bios_types.hdcn31_hpo_dp_stream_encoder.hreg_helper.hdc.h
Detected Declarations
enum dp2_pixel_encodingenum dp2_uncompressed_component_depthfunction dcn31_hpo_dp_stream_enc_enable_streamfunction dcn31_hpo_dp_stream_enc_dp_unblankfunction dcn31_hpo_dp_stream_enc_dp_blankfunction dcn31_hpo_dp_stream_enc_disablefunction dcn31_hpo_dp_stream_enc_set_stream_attributefunction dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_numfunction dcn31_hpo_dp_stream_enc_update_dp_info_packetsfunction dcn31_hpo_dp_stream_enc_stop_dp_info_packetsfunction hpo_dp_is_gsp_enabledfunction dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packetfunction dcn31_hpo_dp_stream_enc_map_stream_to_linkfunction dcn31_hpo_dp_stream_enc_audio_setupfunction dcn31_hpo_dp_stream_enc_audio_enablefunction dcn31_hpo_dp_stream_enc_audio_disablefunction dcn31_hpo_dp_stream_enc_read_statefunction dcn31_set_hblank_min_symbol_widthfunction dcn31_hpo_dp_stream_encoder_construct
Annotated Snippet
if (hw_crtc_timing.flags.Y_ONLY) {
pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY;
if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) {
/* HW testing only, no use case yet.
* Color depth of Y-only could be
* 8, 10, 12, 16 bits
*/
misc1 = misc1 | 0x80; // MISC1[7] = 1
}
}
break;
case PIXEL_ENCODING_YCBCR420:
pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420;
misc1 = misc1 | 0x40; // MISC1[6] = 1
break;
case PIXEL_ENCODING_RGB:
default:
pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444;
break;
}
/* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
* When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
* Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
* and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
*/
if (use_vsc_sdp_for_colorimetry)
misc1 = misc1 | 0x40;
else
misc1 = misc1 & ~0x40;
/* Color depth */
switch (hw_crtc_timing.display_color_depth) {
case COLOR_DEPTH_666:
component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
// MISC0[7:5] = 000
break;
case COLOR_DEPTH_888:
component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_8BPC;
misc0 = misc0 | 0x20; // MISC0[7:5] = 001
break;
case COLOR_DEPTH_101010:
component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_10BPC;
misc0 = misc0 | 0x40; // MISC0[7:5] = 010
break;
case COLOR_DEPTH_121212:
component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_12BPC;
misc0 = misc0 | 0x60; // MISC0[7:5] = 011
break;
default:
component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
break;
}
REG_UPDATE_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,
PIXEL_ENCODING_TYPE, compressed_format,
UNCOMPRESSED_PIXEL_ENCODING, pixel_encoding,
UNCOMPRESSED_COMPONENT_DEPTH, component_depth);
switch (output_color_space) {
case COLOR_SPACE_SRGB:
misc1 = misc1 & ~0x80; /* bit7 = 0*/
break;
case COLOR_SPACE_SRGB_LIMITED:
misc0 = misc0 | 0x8; /* bit3=1 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
break;
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR601_LIMITED:
misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR709_LIMITED:
misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
misc1 = misc1 & ~0x80; /* bit7 = 0*/
if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
break;
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
case COLOR_SPACE_2020_RGB_FULLRANGE:
case COLOR_SPACE_2020_YCBCR_LIMITED:
case COLOR_SPACE_XR_RGB:
case COLOR_SPACE_MSREF_SCRGB:
Annotation
- Immediate include surface: `dc_bios_types.h`, `dcn31_hpo_dp_stream_encoder.h`, `reg_helper.h`, `dc.h`.
- Detected declarations: `enum dp2_pixel_encoding`, `enum dp2_uncompressed_component_depth`, `function dcn31_hpo_dp_stream_enc_enable_stream`, `function dcn31_hpo_dp_stream_enc_dp_unblank`, `function dcn31_hpo_dp_stream_enc_dp_blank`, `function dcn31_hpo_dp_stream_enc_disable`, `function dcn31_hpo_dp_stream_enc_set_stream_attribute`, `function dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num`, `function dcn31_hpo_dp_stream_enc_update_dp_info_packets`, `function dcn31_hpo_dp_stream_enc_stop_dp_info_packets`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.