drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
Extension
.c
Size
29942 bytes
Lines
908
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
					HDMI_DEEP_COLOR_DEPTH, 1,
					HDMI_DEEP_COLOR_ENABLE, 0);
		} else {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
					HDMI_DEEP_COLOR_DEPTH, 1,
					HDMI_DEEP_COLOR_ENABLE, 1);
		}
		break;
	case COLOR_DEPTH_121212:
		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
					HDMI_DEEP_COLOR_DEPTH, 2,
					HDMI_DEEP_COLOR_ENABLE, 0);
		} else {
			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
					HDMI_DEEP_COLOR_DEPTH, 2,
					HDMI_DEEP_COLOR_ENABLE, 1);
		}
		break;
	default:
		break;
	}

	/* When compression active, CD/PP/Phase field shall be zero in GCP */
	if (crtc_timing->flags.DSC) {
		REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
				HDMI_DEEP_COLOR_DEPTH, 0,
				HDMI_DEEP_COLOR_ENABLE, 0);
	}

	/* Configure horizontal active and blank size */
	h_active = crtc_timing->h_addressable + crtc_timing->h_border_left + crtc_timing->h_border_right;
	h_blank = crtc_timing->h_total - h_active;

	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ||
			crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
		h_active /= 2;
		h_blank /= 2;
	}


	REG_SET_2(HDMI_TB_ENC_H_ACTIVE_BLANK, 0,
			HDMI_H_ACTIVE, h_active,
			HDMI_H_BLANK, h_blank);

	/* Configure borrow parameters */
	REG_UPDATE(HDMI_TB_ENC_MODE,
			HDMI_BORROW_MODE, borrow_params->borrow_mode);
	REG_UPDATE(HDMI_TB_ENC_PACKET_CONTROL,
			HDMI_MAX_PACKETS_PER_LINE, borrow_params->audio_packets_line);
	REG_SET_2(HDMI_TB_ENC_HC_ACTIVE_BLANK, 0,
			HDMI_HC_ACTIVE, borrow_params->hc_active_target,
			HDMI_HC_BLANK, borrow_params->hc_blank_target);

	/* Enable transmission of General Control packet on every frame */
	REG_UPDATE_2(HDMI_TB_ENC_VBI_PACKET_CONTROL1,
		HDMI_GC_CONT, 1,
		HDMI_GC_SEND, 1);

	/* Disable Audio Content Protection packet transmission */
	/* TODO: review if this needs to be here */
	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ACP_SEND, 0);


	/* Enable Audio InfoFrame packet transmission. */
	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_SEND, 1);

	/* update double-buffered AUDIO_INFO registers immediately */
	if (enc->afmt && enc->afmt->funcs->audio_info_immediate_update)
		enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

	/* Select line number on which to send Audio InfoFrame packets */
	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_LINE,
				VBI_LINE_0 + 2);

	/* set HDMI GC AVMUTE */
	REG_UPDATE(HDMI_TB_ENC_GC_CONTROL, HDMI_GC_AVMUTE, 0);

	DC_LOG_DEBUG("Exiting [%s]\n", __func__);
}

void hpo_enc401_update_hdmi_info_packet(
	struct dcn401_hpo_frl_stream_encoder *enc401,
	uint32_t packet_index,
	const struct dc_info_packet *info_packet)
{
	uint32_t cont, send, line;

Annotation

Implementation Notes