drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_frl_stream_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_frl_stream_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_frl_stream_encoder.c
Extension
.c
Size
6643 bytes
Lines
208
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2025 Advanced Micro Devices, Inc.

#include "dc_bios_types.h"
#include "core_types.h"
#include "dcn42_hpo_frl_stream_encoder.h"
#include "dcn31/dcn31_apg.h"
#include "dcn401/dcn401_hpo_frl_stream_encoder.h"
#include "dcn30/dcn30_hpo_frl_stream_encoder.h"
#include "reg_helper.h"
#include "hw_shared.h"
#include "dcn_calc_math.h"
#include "dml/dcn30/dcn30_fpu.h"

#undef DC_LOGGER
#define DC_LOGGER \
		enc401->base.ctx->logger

#define DTRACE(str, ...) {DC_LOG_HDMI_FRL(str, ##__VA_ARGS__); }

#define DEBUG_FRL_CAP_CHK 1

#define REG(reg)\
	(enc401->regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	enc401->hpo_se_shift->field_name, enc401->hpo_se_mask->field_name

#define CTX \
	enc401->base.ctx

#define VBI_LINE_0 0

void hpo_enc42_unblank(struct hpo_frl_stream_encoder *enc, int otg_inst)
{
	(void)otg_inst;
	struct dcn401_hpo_frl_stream_encoder *enc401 = DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(enc);

	DC_LOG_HDMI_FRL("Entering [%s]\n", __func__);

	/*make sure FIFO_VIDEO_STREAM_ACTIVE =1*/
	REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
		   FIFO_ENABLE, 0);

	/* Reset */
	REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
		   FIFO_RESET, 1);
	REG_WAIT(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE,
		 1, 10, 1000);
	REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
		   FIFO_RESET, 0);
	REG_WAIT(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE,
		 0, 10, 1000);

	/* Enable HDMI Tribyte Encoder */
	REG_UPDATE(HDMI_TB_ENC_CONTROL,
		   HDMI_TB_ENC_EN, 1);

	/* Enable Clock Ramp Adjuster FIFO */
	REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
		   FIFO_ENABLE, 1);

	DC_LOG_HDMI_FRL("Exiting [%s]\n", __func__);
}

void hpo_enc42_setup_hdmi_audio(
	struct hpo_frl_stream_encoder *enc,
	const struct audio_crtc_info *crtc_info)
{
	struct dcn401_hpo_frl_stream_encoder *enc401 = DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(enc);
	struct frl_audio_clock_info audio_clock_info = {0};

	DC_LOG_DEBUG("Entering [%s]\n", __func__);

	/* TODO:  HDMI_AUDIO_DELAY_EN bit only in DIG -- not in HPO? */
	/* HDMI_AUDIO_PACKET_CONTROL */
	//REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
	//		HDMI_AUDIO_DELAY_EN, 1);

	/* Setup audio in APG - program APG block associated with HPO */
	ASSERT(enc->apg);

	/* HDMI_ACR_PACKET_CONTROL */
	REG_UPDATE_3(HDMI_TB_ENC_ACR_PACKET_CONTROL,
			HDMI_ACR_AUTO_SEND, 1,
			HDMI_ACR_SOURCE, 0,
			HDMI_ACR_AUDIO_PRIORITY, 0);

Annotation

Implementation Notes