drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c- Extension
.c- Size
- 5894 bytes
- Lines
- 220
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dce_hwseq.hreg_helper.hhw_sequencer_private.hcore_types.h
Detected Declarations
function filesfunction dce_pipe_control_lockfunction dce60_pipe_control_lockfunction dce_disable_sram_shut_downfunction dce_underlay_clock_enablefunction enable_hw_base_light_sleepfunction dce_crtc_switch_to_clk_srcfunction dce_use_lut
Annotated Snippet
if (!lock) {
uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
}
}
}
#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_pipe_control_lock(struct dc *dc,
struct pipe_ctx *pipe,
bool lock)
{
/* DCE6 has no BLND_V_UPDATE_LOCK register */
}
#endif
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst,
enum blnd_mode mode)
{
uint32_t feedthrough = 1;
uint32_t blnd_mode = 0;
uint32_t multiplied_mode = 0;
uint32_t alpha_mode = 2;
switch (mode) {
case BLND_MODE_OTHER_PIPE:
feedthrough = 0;
blnd_mode = 1;
alpha_mode = 0;
break;
case BLND_MODE_BLENDING:
feedthrough = 0;
blnd_mode = 2;
alpha_mode = 0;
multiplied_mode = 1;
break;
case BLND_MODE_CURRENT_PIPE:
default:
if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
blnd_inst == 0)
feedthrough = 0;
break;
}
REG_UPDATE(BLND_CONTROL[blnd_inst],
BLND_MODE, blnd_mode);
if (hws->masks->BLND_ALPHA_MODE != 0) {
REG_UPDATE_3(BLND_CONTROL[blnd_inst],
BLND_FEEDTHROUGH_EN, feedthrough,
BLND_ALPHA_MODE, alpha_mode,
BLND_MULTIPLIED_MODE, multiplied_mode);
}
}
static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
{
if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
}
static void dce_underlay_clock_enable(struct dce_hwseq *hws)
{
/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
if (REG(DCFEV_CLOCK_CONTROL))
REG_UPDATE(DCFEV_CLOCK_CONTROL,
DCFEV_CLOCK_ENABLE, 1);
}
static void enable_hw_base_light_sleep(void)
{
/* TODO: implement */
}
static void disable_sw_manual_control_light_sleep(void)
{
/* TODO: implement */
}
void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable)
{
if (enable) {
enable_hw_base_light_sleep();
disable_sw_manual_control_light_sleep();
} else {
dce_disable_sram_shut_down(hws);
Annotation
- Immediate include surface: `dce_hwseq.h`, `reg_helper.h`, `hw_sequencer_private.h`, `core_types.h`.
- Detected declarations: `function files`, `function dce_pipe_control_lock`, `function dce60_pipe_control_lock`, `function dce_disable_sram_shut_down`, `function dce_underlay_clock_enable`, `function enable_hw_base_light_sleep`, `function dce_crtc_switch_to_clk_src`, `function dce_use_lut`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.