drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
Extension: .h
Size: 48981 bytes
Lines: 1315
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dc_types.h

Detected Declarations

struct dce_hwseq_registers
struct dce_hwseq_shift
struct dce_hwseq_mask
struct dce_hwseq
struct pipe_ctx
struct clock_source
enum blnd_mode

Annotated Snippet

struct dce_hwseq_registers {
	uint32_t DCFE_CLOCK_CONTROL[6];
	uint32_t DCFEV_CLOCK_CONTROL;
	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
	uint32_t BLND_V_UPDATE_LOCK[6];
	uint32_t BLND_CONTROL[6];
	uint32_t BLNDV_CONTROL;
	uint32_t CRTC_H_BLANK_START_END[6];
	uint32_t PIXEL_RATE_CNTL[6];
	uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
	/*DCHUB*/
	uint32_t DCHUB_FB_LOCATION;
	uint32_t DCHUB_AGP_BASE;
	uint32_t DCHUB_AGP_BOT;
	uint32_t DCHUB_AGP_TOP;

	uint32_t REFCLK_CNTL;

	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
	uint32_t DCHUBBUB_SDPIF_FB_BASE;
	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
	uint32_t DCHUBBUB_SDPIF_AGP_BASE;
	uint32_t DCHUBBUB_SDPIF_AGP_BOT;
	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
	uint32_t DC_IP_REQUEST_CNTL;
	uint32_t DOMAIN0_PG_CONFIG;
	uint32_t DOMAIN1_PG_CONFIG;
	uint32_t DOMAIN2_PG_CONFIG;
	uint32_t DOMAIN3_PG_CONFIG;
	uint32_t DOMAIN4_PG_CONFIG;
	uint32_t DOMAIN5_PG_CONFIG;
	uint32_t DOMAIN6_PG_CONFIG;
	uint32_t DOMAIN7_PG_CONFIG;
	uint32_t DOMAIN8_PG_CONFIG;
	uint32_t DOMAIN9_PG_CONFIG;
	uint32_t DOMAIN10_PG_CONFIG;
	uint32_t DOMAIN11_PG_CONFIG;
	uint32_t DOMAIN16_PG_CONFIG;
	uint32_t DOMAIN17_PG_CONFIG;
	uint32_t DOMAIN18_PG_CONFIG;
	uint32_t DOMAIN19_PG_CONFIG;
	uint32_t DOMAIN20_PG_CONFIG;
	uint32_t DOMAIN21_PG_CONFIG;
	uint32_t DOMAIN0_PG_STATUS;
	uint32_t DOMAIN1_PG_STATUS;
	uint32_t DOMAIN2_PG_STATUS;
	uint32_t DOMAIN3_PG_STATUS;
	uint32_t DOMAIN4_PG_STATUS;
	uint32_t DOMAIN5_PG_STATUS;
	uint32_t DOMAIN6_PG_STATUS;
	uint32_t DOMAIN7_PG_STATUS;
	uint32_t DOMAIN8_PG_STATUS;
	uint32_t DOMAIN9_PG_STATUS;
	uint32_t DOMAIN10_PG_STATUS;
	uint32_t DOMAIN11_PG_STATUS;
	uint32_t DOMAIN16_PG_STATUS;
	uint32_t DOMAIN17_PG_STATUS;
	uint32_t DOMAIN18_PG_STATUS;
	uint32_t DOMAIN19_PG_STATUS;
	uint32_t DOMAIN20_PG_STATUS;
	uint32_t DOMAIN21_PG_STATUS;
	uint32_t DIO_MEM_PWR_CTRL;
	uint32_t DCCG_GATE_DISABLE_CNTL;
	uint32_t DCCG_GATE_DISABLE_CNTL2;
	uint32_t DCFCLK_CNTL;
	uint32_t MICROSECOND_TIME_BASE_DIV;
	uint32_t MILLISECOND_TIME_BASE_DIV;
	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
	uint32_t RBBMIF_TIMEOUT_DIS;
	uint32_t RBBMIF_TIMEOUT_DIS_2;
	uint32_t DCHUBBUB_CRC_CTRL;
	uint32_t DPP_TOP0_DPP_CRC_CTRL;
	uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
	uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
	uint32_t DPP_TOP0_DPP_CRC_VAL_R;
	uint32_t DPP_TOP0_DPP_CRC_VAL_G;
	uint32_t DPP_TOP0_DPP_CRC_VAL_B;
	uint32_t DPP_TOP0_DPP_CRC_VAL_A;
	uint32_t MPC_CRC_CTRL;
	uint32_t MPC_CRC_RESULT_GB;
	uint32_t MPC_CRC_RESULT_C;
	uint32_t MPC_CRC_RESULT_AR;
	uint32_t MPC_CRC_RESULT_R;
	uint32_t MPC_CRC_RESULT_G;
	uint32_t MPC_CRC_RESULT_B;
	uint32_t MPC_CRC_RESULT_A;
	uint32_t D1VGA_CONTROL;
	uint32_t D2VGA_CONTROL;
	uint32_t D3VGA_CONTROL;
	uint32_t D4VGA_CONTROL;

Annotation

Immediate include surface: `dc_types.h`.
Detected declarations: `struct dce_hwseq_registers`, `struct dce_hwseq_shift`, `struct dce_hwseq_mask`, `struct dce_hwseq`, `struct pipe_ctx`, `struct clock_source`, `enum blnd_mode`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.