drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

Extension

.h

Size

7910 bytes

Lines

224

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• core_types.h
• hw_sequencer_private.h

Detected Declarations

• struct dc

Annotated Snippet

#ifndef __DC_HWSS_DCN10_H__
#define __DC_HWSS_DCN10_H__

#include "core_types.h"
#include "hw_sequencer_private.h"

struct dc;

void dcn10_hw_sequencer_construct(struct dc *dc);

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
void dcn10_calc_vupdate_position(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		uint32_t *start_line,
		uint32_t *end_line);
void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
enum dc_status dcn10_enable_stream_timing(
		struct pipe_ctx *pipe_ctx,
		struct dc_state *context,
		struct dc *dc);
void dcn10_optimize_bandwidth(
		struct dc *dc,
		struct dc_state *context);
void dcn10_prepare_bandwidth(
		struct dc *dc,
		struct dc_state *context);
void dcn10_wait_for_pipe_update_if_needed(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		bool is_surface_update_only);
void dcn10_set_wait_for_update_needed_for_pipe(
	struct dc *dc,
	struct pipe_ctx *pipe_ctx);
void dcn10_pipe_control_lock(
	struct dc *dc,
	struct pipe_ctx *pipe,
	bool lock);
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
void dcn10_blank_pixel_data(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		bool blank);
void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
		struct dc_link_settings *link_settings);
void dcn10_program_output_csc(struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		enum dc_color_space colorspace,
		uint16_t *matrix,
		int opp_id);
bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
				const struct dc_stream_state *stream);
bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
			const struct dc_plane_state *plane_state);
void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
void dcn10_reset_hw_ctx_wrap(
		struct dc *dc,
		struct dc_state *context);
void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
void dcn10_lock_all_pipes(
		struct dc *dc,
		struct dc_state *context,
		bool lock);
void dcn10_post_unlock_program_front_end(
		struct dc *dc,
		struct dc_state *context);
void dcn10_hubp_pg_control(
		struct dce_hwseq *hws,
		unsigned int hubp_inst,
		bool power_on);
void dcn10_dpp_pg_control(
		struct dce_hwseq *hws,
		unsigned int dpp_inst,
		bool power_on);
void dcn10_enable_power_gating_plane(
	struct dce_hwseq *hws,
	bool enable);
void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
void dcn10_disable_vga(
	struct dce_hwseq *hws);
void dcn10_program_pipe(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		struct dc_state *context);
void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
void dcn10_init_hw(struct dc *dc);
void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
void dcn10_power_down_on_boot(struct dc *dc);
enum dc_status dce110_apply_ctx_to_hw(

Annotation

• Immediate include surface: `core_types.h`, `hw_sequencer_private.h`.
• Detected declarations: `struct dc`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.