drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
Extension
.c
Size
10045 bytes
Lines
302
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (abm->funcs && abm->funcs->set_pipe_ex) {
			abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,
					panel_cntl->inst, panel_cntl->pwrseq_inst);
		} else {
			dcn21_dmub_abm_set_pipe(abm,
						otg_inst,
						SET_ABM_PIPE_IMMEDIATELY_DISABLE,
						panel_cntl->inst,
						panel_cntl->pwrseq_inst);
		}
		panel_cntl->funcs->store_backlight_level(panel_cntl);
	}
}

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
{
	struct abm *abm = pipe_ctx->stream_res.abm;
	struct timing_generator *tg = pipe_ctx->stream_res.tg;
	struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
	struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;
	uint32_t otg_inst;

	if (!abm || !tg || !panel_cntl)
		return;

	otg_inst = tg->inst;

	if (dmcu) {
		dce110_set_pipe(pipe_ctx);
		return;
	}

	if (abm->funcs && abm->funcs->set_pipe_ex) {
		abm->funcs->set_pipe_ex(abm,
					otg_inst,
					SET_ABM_PIPE_NORMAL,
					panel_cntl->inst,
					panel_cntl->pwrseq_inst);
	} else {
			dcn21_dmub_abm_set_pipe(abm, otg_inst,
				  SET_ABM_PIPE_NORMAL,
				  panel_cntl->inst,
				  panel_cntl->pwrseq_inst);
	}
}

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
	struct set_backlight_level_params *backlight_level_params)
{
	struct dc_context *dc = pipe_ctx->stream->ctx;
	struct abm *abm = pipe_ctx->stream_res.abm;
	struct timing_generator *tg = pipe_ctx->stream_res.tg;
	struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
	uint32_t otg_inst;
	uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
	uint32_t frame_ramp = backlight_level_params->frame_ramp;

	if (!abm || !tg || !panel_cntl)
		return false;

	otg_inst = tg->inst;

	if (dc->dc->res_pool->dmcu) {
		dce110_set_backlight_level(pipe_ctx, backlight_level_params);
		return true;
	}

	if (abm->funcs && abm->funcs->set_pipe_ex) {
		abm->funcs->set_pipe_ex(abm,
					otg_inst,
					SET_ABM_PIPE_NORMAL,
					panel_cntl->inst,
					panel_cntl->pwrseq_inst);
	} else {
			dcn21_dmub_abm_set_pipe(abm,
				  otg_inst,
				  SET_ABM_PIPE_NORMAL,
				  panel_cntl->inst,
				  panel_cntl->pwrseq_inst);
	}

	if (abm->funcs && abm->funcs->set_backlight_level_pwm)
		abm->funcs->set_backlight_level_pwm(abm, backlight_pwm_u16_16,
			frame_ramp, 0, panel_cntl->inst);
	else
		dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);

	return true;
}

Annotation

Implementation Notes