drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
Extension
.h
Size
3979 bytes
Lines
120
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DC_HWSS_DCN30_H__
#define __DC_HWSS_DCN30_H__

#include "hw_sequencer_private.h"

struct dc;
struct dc_underflow_debug_data;

void dcn30_init_hw(struct dc *dc);
void dcn30_program_all_writeback_pipes_in_tree(
		struct dc *dc,
		const struct dc_stream_state *stream,
		struct dc_state *context);
void dcn30_update_writeback(
		struct dc *dc,
		struct dc_writeback_info *wb_info,
		struct dc_state *context);
void dcn30_enable_writeback(
		struct dc *dc,
		struct dc_writeback_info *wb_info,
		struct dc_state *context);
void dcn30_disable_writeback(
		struct dc *dc,
		unsigned int dwb_pipe_inst);

bool dcn30_mmhubbub_warmup(
	struct dc *dc,
	unsigned int num_dwb,
	struct dc_writeback_info *wb_info);

void dcn30_log_color_state(struct dc *dc,
			   struct dc_log_buffer_ctx *log_ctx);

bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
		const struct dc_plane_state *plane_state);

bool dcn30_set_input_transfer_func(struct dc *dc,
				struct pipe_ctx *pipe_ctx,
				const struct dc_plane_state *plane_state);

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);

bool dcn30_set_output_transfer_func(struct dc *dc,
				struct pipe_ctx *pipe_ctx,
				const struct dc_stream_state *stream);
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

enum dc_status dcn30_setup_hdmi_frl_link(
		struct dc_link *link,
		int hpo_inst,
		enum clock_source_id frl_phy_clock_source_id);
void dcn30_hw_set_fva_vrr_adj(struct dc *dc, struct pipe_ctx **pipe_ctx, int num_pipes,
		struct fva_adj *fva_adj,
		struct dc_crtc_timing_adjust *vrr_adj);

int dcn30_hw_get_max_fva_factor(struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		struct dc_crtc_timing *timing,
		unsigned int max_pixel_clock);

bool dcn30_does_plane_fit_in_mall(struct dc *dc,
		unsigned int pitch,
		unsigned int height,
		enum surface_pixel_format format,
		struct dc_cursor_attributes *cursor_attr);

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);

void dcn30_hardware_release(struct dc *dc);

void dcn30_set_disp_pattern_generator(const struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		enum controller_dp_test_pattern test_pattern,
		enum controller_dp_color_space color_space,
		enum dc_color_depth color_depth,
		const struct tg_color *solid_color,
		int width, int height, int offset);

void dcn30_set_hubp_blank(const struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		bool blank_enable);

void dcn30_prepare_bandwidth(struct dc *dc,
	struct dc_state *context);

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);

void dcn30_get_underflow_debug_data(const struct dc *dc,

Annotation

Implementation Notes