drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

Extension

.h

Size

1820 bytes

Lines

55

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• dc.h
• hw_sequencer_private.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DC_HWSS_DCN42_H__
#define __DC_HWSS_DCN42_H__

#include "dc.h"
#include "hw_sequencer_private.h"

void dcn42_init_hw(struct dc *dc);
void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

void dcn42_program_cm_hist(
	struct dc *dc,
	struct pipe_ctx *pipe_ctx,
	const struct dc_plane_state *plane_state);

bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx,
	const struct dc_plane_state *plane_state);

void dcn42_populate_mcm_luts(struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		struct dc_cm2_func_luts mcm_luts,
		bool lut_bank_a);

bool dcn42_program_rmcm_luts(
	struct hubp *hubp,
	struct pipe_ctx *pipe_ctx,
	enum dc_cm2_transfer_func_source lut3d_src,
	struct dc_cm2_func_luts *mcm_luts,
	struct mpc *mpc,
	bool lut_bank_a,
	int mpcc_id);
void dcn42_hardware_release(struct dc *dc);

void dcn42_prepare_bandwidth(
	struct dc *dc,
	struct dc_state *context);
void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context);
void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
		struct pg_block_update *update_state);
void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
		struct pg_block_update *update_state);
void dcn42_hw_block_power_down(struct dc *dc,
	struct pg_block_update *update_state);
void dcn42_hw_block_power_up(struct dc *dc,
		struct pg_block_update *update_state);
void dcn42_root_clock_control(struct dc *dc,
		struct pg_block_update *update_state, bool power_on);
void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock);
void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params);
void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
void dcn42_power_down_on_boot(struct dc *dc);
#endif

Annotation

• Immediate include surface: `dc.h`, `hw_sequencer_private.h`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.