drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h- Extension
.h- Size
- 78810 bytes
- Lines
- 2479
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dc_types.hinc/clock_source.hinc/hw/timing_generator.hinc/hw/opp.hinc/hw/link_encoder.hinc/core_status.hinc/hw/hw_shared.hdsc/dsc.hlink_service_types.h
Detected Declarations
struct pipe_ctxstruct dc_statestruct dc_stream_statusstruct dc_writeback_infostruct dchub_init_datastruct dc_static_screen_paramsstruct resource_poolstruct dc_phy_addr_space_configstruct dc_virtual_addr_space_configstruct dppstruct dce_hwseqstruct link_resourcestruct dc_dmub_cmdstruct pg_block_updatestruct drr_paramsstruct dc_underflow_debug_datastruct dsc_optc_configstruct vm_system_aperture_paramstruct dc_measured_memory_qosstruct stream_encoderstruct hpo_dp_stream_encoderstruct hpo_frl_stream_encoderstruct link_training_settingsstruct dc_linkstruct dc_crtc_timingstruct subvp_pipe_control_lock_fast_paramsstruct pipe_control_lock_paramsstruct set_flip_control_gsl_paramsstruct program_triplebuffer_paramsstruct update_plane_addr_paramsstruct set_input_transfer_func_paramsstruct program_gamut_remap_paramsstruct hubp_enable_3dlut_fl_paramsstruct tg_setup_vertical_interrupt0_paramsstruct update_info_frame_paramsstruct program_manual_trigger_paramsstruct send_dmcub_cmd_paramsstruct setup_dpp_paramsstruct program_bias_and_scale_paramsstruct set_output_transfer_func_paramsstruct update_visual_confirm_paramsstruct power_on_mpc_mem_pwr_paramsstruct set_output_csc_paramsstruct set_ocsc_default_paramsstruct subvp_save_surf_addrstruct wait_for_dcc_meta_propagation_paramsstruct dmub_hw_control_lock_fast_paramsstruct program_surface_config_params
Annotated Snippet
struct subvp_pipe_control_lock_fast_params {
struct dc *dc;
bool lock;
bool subvp_immediate_flip;
};
struct pipe_control_lock_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
bool lock;
};
struct set_flip_control_gsl_params {
struct hubp *hubp;
bool flip_immediate;
};
struct program_triplebuffer_params {
const struct dc *dc;
struct pipe_ctx *pipe_ctx;
bool enableTripleBuffer;
};
struct update_plane_addr_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
};
struct set_input_transfer_func_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
struct dc_plane_state *plane_state;
};
struct program_gamut_remap_params {
struct pipe_ctx *pipe_ctx;
};
struct hubp_enable_3dlut_fl_params {
struct hubp *hubp;
};
struct tg_setup_vertical_interrupt0_params {
struct timing_generator *tg;
uint32_t start_line;
uint32_t end_line;
};
struct update_info_frame_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
};
struct program_manual_trigger_params {
struct pipe_ctx *pipe_ctx;
};
struct send_dmcub_cmd_params {
struct dc_context *ctx;
union dmub_rb_cmd *cmd;
enum dm_dmub_wait_type wait_type;
};
struct setup_dpp_params {
struct pipe_ctx *pipe_ctx;
};
struct program_bias_and_scale_params {
struct pipe_ctx *pipe_ctx;
};
struct set_output_transfer_func_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
const struct dc_stream_state *stream;
};
struct update_visual_confirm_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
int mpcc_id;
};
struct power_on_mpc_mem_pwr_params {
struct mpc *mpc;
int mpcc_id;
bool power_on;
};
struct set_output_csc_params {
Annotation
- Immediate include surface: `dc_types.h`, `inc/clock_source.h`, `inc/hw/timing_generator.h`, `inc/hw/opp.h`, `inc/hw/link_encoder.h`, `inc/core_status.h`, `inc/hw/hw_shared.h`, `dsc/dsc.h`.
- Detected declarations: `struct pipe_ctx`, `struct dc_state`, `struct dc_stream_status`, `struct dc_writeback_info`, `struct dchub_init_data`, `struct dc_static_screen_params`, `struct resource_pool`, `struct dc_phy_addr_space_config`, `struct dc_virtual_addr_space_config`, `struct dpp`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.