drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

Extension

.h

Size

9338 bytes

Lines

249

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• dc_types.h
• hw_sequencer.h

Detected Declarations

• struct dce_hwseq_wa
• struct hwseq_wa_state
• struct pipe_ctx
• struct dc_state
• struct dc_stream_status
• struct dc_writeback_info
• struct dchub_init_data
• struct dc_static_screen_params
• struct resource_pool
• struct resource_context
• struct stream_resource
• struct dc_phy_addr_space_config
• struct dc_virtual_addr_space_config
• struct hubp
• struct dpp
• struct dce_hwseq
• struct timing_generator
• struct tg_color
• struct output_pixel_processor
• struct mpcc_blnd_cfg
• struct hwseq_private_funcs
• struct dce_hwseq
• enum pipe_gating_control

Annotated Snippet

struct dce_hwseq_wa {
	bool blnd_crtc_trigger;
	bool DEGVIDCN10_253;
	bool false_optc_underflow;
	bool DEGVIDCN10_254;
	bool DEGVIDCN21;
	bool disallow_self_refresh_during_multi_plane_transition;
	bool dp_hpo_and_otg_sequence;
	bool wait_hubpret_read_start_during_mpo_transition;
};

struct hwseq_wa_state {
	bool DEGVIDCN10_253_applied;
	bool disallow_self_refresh_during_multi_plane_transition_applied;
	unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
	bool skip_blank_stream;
};

struct pipe_ctx;
struct dc_state;
struct dc_stream_status;
struct dc_writeback_info;
struct dchub_init_data;
struct dc_static_screen_params;
struct resource_pool;
struct resource_context;
struct stream_resource;
struct dc_phy_addr_space_config;
struct dc_virtual_addr_space_config;
struct hubp;
struct dpp;
struct dce_hwseq;
struct timing_generator;
struct tg_color;
struct output_pixel_processor;
struct mpcc_blnd_cfg;

struct hwseq_private_funcs {

	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
	void (*init_pipes)(struct dc *dc, struct dc_state *context);
	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
	void (*plane_atomic_disconnect)(struct dc *dc,
			struct dc_state *state,
			struct pipe_ctx *pipe_ctx);
	void (*plane_atomic_disconnect_sequence)(struct dc *dc,
			struct dc_state *state,
			struct pipe_ctx *pipe_ctx,
			struct block_sequence_state *seq_state);
	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
	void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,
			struct block_sequence_state *seq_state);
	bool (*set_input_transfer_func)(struct dc *dc,
				struct pipe_ctx *pipe_ctx,
				const struct dc_plane_state *plane_state);
	bool (*set_output_transfer_func)(struct dc *dc,
				struct pipe_ctx *pipe_ctx,
				const struct dc_stream_state *stream);
	void (*power_down)(struct dc *dc);
	void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
					bool clock_gating);
	bool (*enable_display_power_gating)(struct dc *dc,
					uint8_t controller_id,
					struct dc_bios *dcb,
					enum pipe_gating_control power_gating);
	void (*blank_pixel_data)(struct dc *dc,
			struct pipe_ctx *pipe_ctx,
			bool blank);
	void (*blank_pixel_data_sequence)(struct dc *dc,
			struct pipe_ctx *pipe_ctx,
			bool blank,
			struct block_sequence_state *seq_state);
	enum dc_status (*enable_stream_timing)(
			struct pipe_ctx *pipe_ctx,
			struct dc_state *context,
			struct dc *dc);
	void (*edp_backlight_control)(struct dc_link *link,
			bool enable);
	void (*setup_vupdate_interrupt)(struct dc *dc,
			struct pipe_ctx *pipe_ctx);
	void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,
		struct block_sequence_state *seq_state);
	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
	void (*disable_vga)(struct dce_hwseq *hws);
	void (*bios_golden_init)(struct dc *dc);
	void (*plane_atomic_power_down)(struct dc *dc,
			struct dpp *dpp,
			struct hubp *hubp);

Annotation

• Immediate include surface: `dc_types.h`, `hw_sequencer.h`.
• Detected declarations: `struct dce_hwseq_wa`, `struct hwseq_wa_state`, `struct pipe_ctx`, `struct dc_state`, `struct dc_stream_status`, `struct dc_writeback_info`, `struct dchub_init_data`, `struct dc_static_screen_params`, `struct resource_pool`, `struct resource_context`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.