drivers/gpu/drm/amd/display/dc/inc/clock_source.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/clock_source.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
Extension
.h
Size
5960 bytes
Lines
192
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct spread_spectrum_data {
	uint32_t percentage;		/*> In unit of 0.01% or 0.001%*/
	uint32_t percentage_divider;	/*> 100 or 1000	*/
	uint32_t freq_range_khz;
	uint32_t modulation_freq_hz;

	struct spread_spectrum_flags flags;
};

struct delta_sigma_data {
	uint32_t feedback_amount;
	uint32_t nfrac_amount;
	uint32_t ds_frac_size;
	uint32_t ds_frac_amount;
};

/**
 *  Pixel Clock Parameters structure
 *  These parameters are required as input
 *  when calculating Pixel Clock Dividers for requested Pixel Clock
 */
struct pixel_clk_flags {
	uint32_t ENABLE_SS:1;
	uint32_t DISPLAY_BLANKED:1;
	uint32_t PROGRAM_PIXEL_CLOCK:1;
	uint32_t PROGRAM_ID_CLOCK:1;
	uint32_t SUPPORT_YCBCR420:1;
};

/**
 *  Display Port HW De spread of Reference Clock related Parameters structure
 *  Store it once at boot for later usage
  */
struct csdp_ref_clk_ds_params {
	bool hw_dso_n_dp_ref_clk;
/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
	uint32_t avg_dp_ref_clk_khz;
/* Average DP Reference clock (in KHz)*/
	uint32_t ss_percentage_on_dp_ref_clk;
/* DP Reference clock SS percentage
 * (not to be mixed with DP IDCLK SS from PLL Settings)*/
	uint32_t ss_percentage_divider;
/* DP Reference clock SS percentage divider */
};

struct pixel_clk_params {
	uint32_t requested_pix_clk_100hz;
/*> Requested Pixel Clock
 * (based on Video Timing standard used for requested mode)*/
	uint32_t requested_sym_clk; /* in KHz */
/*> Requested Sym Clock (relevant only for display port)*/
	uint32_t dp_ref_clk; /* in KHz */
/*> DP reference clock - calculated only for DP signal for specific cases*/
	struct graphics_object_id encoder_object_id;
/*> Encoder object Id - needed by VBIOS Exec table*/
	enum signal_type signal_type;
/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
	enum controller_id controller_id;
/*> ControllerId - which controller using this PLL*/
	enum dc_color_depth color_depth;
	struct csdp_ref_clk_ds_params de_spread_params;
/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
	enum dc_pixel_encoding pixel_encoding;
	struct pixel_clk_flags flags;
	uint32_t dio_se_pix_per_cycle;
};

/**
 *  Pixel Clock Dividers structure with desired Pixel Clock
 *  (adjusted after VBIOS exec table),
 *  with actually calculated Clock and reference Crystal frequency
 */
struct pll_settings {
	uint32_t actual_pix_clk_100hz;
	uint32_t adjusted_pix_clk_100hz;
	uint32_t calculated_pix_clk_100hz;
	uint32_t vco_freq;
	uint32_t reference_freq;
	uint32_t reference_divider;
	uint32_t feedback_divider;
	uint32_t fract_feedback_divider;
	uint32_t pix_clk_post_divider;
	uint32_t ss_percentage;
	bool use_external_clk;
};

struct calc_pll_clock_source_init_data {
	struct dc_bios *bp;
	uint32_t min_pix_clk_pll_post_divider;
	uint32_t max_pix_clk_pll_post_divider;

Annotation

Implementation Notes