drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h- Extension
.h- Size
- 26501 bytes
- Lines
- 650
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
bw_fixed.hdml/display_mode_lib.h
Detected Declarations
struct dcstruct dc_statestruct dcn_bw_internal_varsstruct dcn_soc_bounding_boxstruct dcn_ip_paramsenum dcn_bw_defs
Annotated Snippet
struct dcn_bw_internal_vars {
float voltage[number_of_states_plus_one + 1];
float max_dispclk[number_of_states_plus_one + 1];
float max_dppclk[number_of_states_plus_one + 1];
float dcfclk_per_state[number_of_states_plus_one + 1];
float phyclk_per_state[number_of_states_plus_one + 1];
float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
float sr_exit_time;
float sr_enter_plus_exit_time;
float dram_clock_change_latency;
float urgent_latency;
float write_back_latency;
float percent_of_ideal_drambw_received_after_urg_latency;
float dcfclkv_max0p9;
float dcfclkv_nom0p8;
float dcfclkv_mid0p72;
float dcfclkv_min0p65;
float max_dispclk_vmax0p9;
float max_dppclk_vmax0p9;
float max_dispclk_vnom0p8;
float max_dppclk_vnom0p8;
float max_dispclk_vmid0p72;
float max_dppclk_vmid0p72;
float max_dispclk_vmin0p65;
float max_dppclk_vmin0p65;
float socclk;
float fabric_and_dram_bandwidth_vmax0p9;
float fabric_and_dram_bandwidth_vnom0p8;
float fabric_and_dram_bandwidth_vmid0p72;
float fabric_and_dram_bandwidth_vmin0p65;
float round_trip_ping_latency_cycles;
float urgent_out_of_order_return_per_channel;
float number_of_channels;
float vmm_page_size;
float return_bus_width;
float rob_buffer_size_in_kbyte;
float det_buffer_size_in_kbyte;
float dpp_output_buffer_pixels;
float opp_output_buffer_lines;
float pixel_chunk_size_in_kbyte;
float pte_chunk_size;
float meta_chunk_size;
float writeback_chunk_size;
enum dcn_bw_defs odm_capability;
enum dcn_bw_defs dsc_capability;
float line_buffer_size;
enum dcn_bw_defs is_line_buffer_bpp_fixed;
float line_buffer_fixed_bpp;
float max_line_buffer_lines;
float writeback_luma_buffer_size;
float writeback_chroma_buffer_size;
float max_num_dpp;
float max_num_writeback;
float max_dchub_topscl_throughput;
float max_pscl_tolb_throughput;
float max_lb_tovscl_throughput;
float max_vscl_tohscl_throughput;
float max_hscl_ratio;
float max_vscl_ratio;
float max_hscl_taps;
float max_vscl_taps;
float under_scan_factor;
float phyclkv_max0p9;
float phyclkv_nom0p8;
float phyclkv_mid0p72;
float phyclkv_min0p65;
float pte_buffer_size_in_requests;
float dispclk_ramping_margin;
float downspreading;
float max_inter_dcn_tile_repeaters;
enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
int mode;
float viewport_width[number_of_planes_minus_one + 1];
float htotal[number_of_planes_minus_one + 1];
float vtotal[number_of_planes_minus_one + 1];
float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
float vactive[number_of_planes_minus_one + 1];
float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
float viewport_height[number_of_planes_minus_one + 1];
enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
float dcc_rate[number_of_planes_minus_one + 1];
enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
float lb_bit_per_pixel[number_of_planes_minus_one + 1];
enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
enum dcn_bw_defs output[number_of_planes_minus_one + 1];
float scaler_rec_out_width[number_of_planes_minus_one + 1];
Annotation
- Immediate include surface: `bw_fixed.h`, `dml/display_mode_lib.h`.
- Detected declarations: `struct dc`, `struct dc_state`, `struct dcn_bw_internal_vars`, `struct dcn_soc_bounding_box`, `struct dcn_ip_params`, `enum dcn_bw_defs`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.