drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
Extension: .h
Size: 13972 bytes
Lines: 437
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dc.h
core_types.h
dm_pp_smu.h

Detected Declarations

struct dcn3_clk_internal
struct dcn35_clk_internal
struct dcn301_clk_internal
struct dcn42_clk_internal
struct dcn42b_clk_internal
struct clk_limit_table_entry
struct clk_limit_num_entries
struct clk_limit_table
struct wm_range_table_entry
struct nv_wm_range_entry
struct clk_log_info
struct clk_state_registers_and_bypass
struct rv1_clk_internal
struct rn_clk_internal
struct clk_state_registers
struct clk_bypass
struct wm_table
struct dummy_pstate_entry
struct clk_bw_params
struct clk_states
struct clk_mgr_funcs
struct clk_mgr
struct dccg
enum clk_type

Annotated Snippet

struct dcn3_clk_internal {
	int dummy;
//	TODO:
	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
	uint32_t CLK1_CLK4_CURRENT_CNT;
	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider
	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow

	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

	uint32_t CLK4_CLK0_CURRENT_CNT; //fclk
};

struct dcn35_clk_internal {
	int dummy;
	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
	uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk
	//uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk
	//uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk
	uint32_t CLK1_CLK3_DS_CNTL;	    //dcf_deep_sleep_divider
	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow

	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
	uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass
};

struct dcn301_clk_internal {
	int dummy;
	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider
	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow

	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
};

struct dcn42_clk_internal {
	int dummy;
	uint32_t CLK8_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK8_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK8_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK8_CLK3_CURRENT_CNT; //dcfclk
	uint32_t CLK8_CLK4_CURRENT_CNT; //dtbclk
	uint32_t CLK8_CLK0_DS_CNTL;	    //dispclk deep_sleep_divider
	uint32_t CLK8_CLK1_DS_CNTL;	    //dppclk deep_sleep_divider
	uint32_t CLK8_CLK2_DS_CNTL;	    //dprefclk deep_sleep_divider
	uint32_t CLK8_CLK3_DS_CNTL;	    //dcfclk deep_sleep_divider
	uint32_t CLK8_CLK4_DS_CNTL;	    //dtbclk deep_sleep_divider
	uint32_t CLK8_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK8_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK8_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK8_CLK3_BYPASS_CNTL; //dcfclk bypass
	uint32_t CLK8_CLK4_BYPASS_CNTL; //dtbclk bypass
	uint32_t CLK8_CLK_TICK_CNT__TIMER_THRESHOLD;
};

struct dcn42b_clk_internal {
	int dummy;
	uint32_t CLK5_CLK0_CURRENT_CNT; //dispclk
	uint32_t CLK5_CLK1_CURRENT_CNT; //dppclk
	uint32_t CLK5_CLK2_CURRENT_CNT; //dprefclk
	uint32_t CLK5_CLK3_CURRENT_CNT; //dcfclk
	//uint32_t CLK5_CLK4_CURRENT_CNT; //dtbclk
	uint32_t CLK5_CLK0_DS_CNTL;	    //dispclk deep_sleep_divider
	uint32_t CLK5_CLK1_DS_CNTL;	    //dppclk deep_sleep_divider
	uint32_t CLK5_CLK2_DS_CNTL;	    //dprefclk deep_sleep_divider
	uint32_t CLK5_CLK3_DS_CNTL;	    //dcfclk deep_sleep_divider
	uint32_t CLK5_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
	//uint32_t CLK8_CLK4_DS_CNTL;	    //dtbclk deep_sleep_divider
	uint32_t CLK5_CLK0_BYPASS_CNTL; //dispclk bypass
	uint32_t CLK5_CLK1_BYPASS_CNTL; //dppclk bypass
	uint32_t CLK5_CLK2_BYPASS_CNTL; //dprefclk bypass
	uint32_t CLK5_CLK3_BYPASS_CNTL; //dcfclk bypass

Annotation

Immediate include surface: `dc.h`, `core_types.h`, `dm_pp_smu.h`.
Detected declarations: `struct dcn3_clk_internal`, `struct dcn35_clk_internal`, `struct dcn301_clk_internal`, `struct dcn42_clk_internal`, `struct dcn42b_clk_internal`, `struct clk_limit_table_entry`, `struct clk_limit_num_entries`, `struct clk_limit_table`, `struct wm_range_table_entry`, `struct nv_wm_range_entry`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.