drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
Extension
.h
Size
18486 bytes
Lines
577
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct clk_mgr_registers {
	uint32_t DPREFCLK_CNTL;
	uint32_t DENTIST_DISPCLK_CNTL;

	uint32_t CLK4_CLK2_CURRENT_CNT;
	uint32_t CLK4_CLK_PLL_REQ;

	uint32_t CLK4_CLK0_CURRENT_CNT;

	uint32_t CLK3_CLK2_DFS_CNTL;
	uint32_t CLK3_CLK_PLL_REQ;

	uint32_t CLK0_CLK2_DFS_CNTL;
	uint32_t CLK0_CLK_PLL_REQ;

	uint32_t CLK1_CLK_PLL_REQ;
	uint32_t CLK1_CLK0_DFS_CNTL;
	uint32_t CLK1_CLK1_DFS_CNTL;
	uint32_t CLK1_CLK2_DFS_CNTL;
	uint32_t CLK1_CLK3_DFS_CNTL;
	uint32_t CLK1_CLK4_DFS_CNTL;
	uint32_t CLK1_CLK5_DFS_CNTL;
	uint32_t CLK2_CLK2_DFS_CNTL;

	uint32_t CLK1_CLK0_CURRENT_CNT;
	uint32_t CLK1_CLK1_CURRENT_CNT;
	uint32_t CLK1_CLK2_CURRENT_CNT;
	uint32_t CLK1_CLK3_CURRENT_CNT;
	uint32_t CLK1_CLK4_CURRENT_CNT;
	uint32_t CLK1_CLK5_CURRENT_CNT;

	uint32_t CLK0_CLK0_DFS_CNTL;
	uint32_t CLK0_CLK1_DFS_CNTL;
	uint32_t CLK0_CLK3_DFS_CNTL;
	uint32_t CLK0_CLK4_DFS_CNTL;
	uint32_t CLK1_CLK0_BYPASS_CNTL;
	uint32_t CLK1_CLK1_BYPASS_CNTL;
	uint32_t CLK1_CLK2_BYPASS_CNTL;
	uint32_t CLK1_CLK3_BYPASS_CNTL;
	uint32_t CLK1_CLK4_BYPASS_CNTL;
	uint32_t CLK1_CLK5_BYPASS_CNTL;

	uint32_t CLK1_CLK0_DS_CNTL;
	uint32_t CLK1_CLK1_DS_CNTL;
	uint32_t CLK1_CLK2_DS_CNTL;
	uint32_t CLK1_CLK3_DS_CNTL;
	uint32_t CLK1_CLK4_DS_CNTL;
	uint32_t CLK1_CLK5_DS_CNTL;

	uint32_t CLK1_CLK0_ALLOW_DS;
	uint32_t CLK1_CLK1_ALLOW_DS;
	uint32_t CLK1_CLK2_ALLOW_DS;
	uint32_t CLK1_CLK3_ALLOW_DS;
	uint32_t CLK1_CLK4_ALLOW_DS;
	uint32_t CLK1_CLK5_ALLOW_DS;
	uint32_t CLK5_spll_field_8;
	uint32_t CLK6_spll_field_8;
	CLK42_REG_LIST(8, uint32_t)
	CLK42_REG_LIST(5, uint32_t)
};

struct clk_mgr_shift {
	CLK_REG_FIELD_LIST(uint8_t)
	CLK20_REG_FIELD_LIST(uint8_t)
	CLK42_REG_FIELD_LIST(uint8_t)
};

struct clk_mgr_mask {
	CLK_REG_FIELD_LIST(uint32_t)
	CLK20_REG_FIELD_LIST(uint32_t)
	CLK42_REG_FIELD_LIST(uint32_t)
};

enum clock_type {
	clock_type_dispclk = 1,
	clock_type_dcfclk,
	clock_type_socclk,
	clock_type_pixelclk,
	clock_type_phyclk,
	clock_type_dppclk,
	clock_type_fclk,
	clock_type_dcfdsclk,
	clock_type_dscclk,
	clock_type_uclk,
	clock_type_dramclk,
	clock_type_dprefclk,
	clock_type_dtbclk,
};

struct clk_mgr_internal {

Annotation

Implementation Notes