drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
Extension
.h
Size
10391 bytes
Lines
354
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dp_dto_params {
	int otg_inst;
	enum signal_type signal;
	enum streamclk_source clk_src;
	uint64_t pixclk_hz;
	uint64_t refclk_hz;
};

enum pixel_rate_div {
   PIXEL_RATE_DIV_BY_1 = 0,
   PIXEL_RATE_DIV_BY_2 = 1,
   PIXEL_RATE_DIV_BY_4 = 3,
   PIXEL_RATE_DIV_NA = 0xF
};

struct dcn_dccg_reg_state {
	uint32_t dc_mem_global_pwr_req_cntl;
	uint32_t dccg_audio_dtbclk_dto_modulo;
	uint32_t dccg_audio_dtbclk_dto_phase;
	uint32_t dccg_audio_dto_source;
	uint32_t dccg_audio_dto0_module;
	uint32_t dccg_audio_dto0_phase;
	uint32_t dccg_audio_dto1_module;
	uint32_t dccg_audio_dto1_phase;
	uint32_t dccg_cac_status;
	uint32_t dccg_cac_status2;
	uint32_t dccg_disp_cntl_reg;
	uint32_t dccg_ds_cntl;
	uint32_t dccg_ds_dto_incr;
	uint32_t dccg_ds_dto_modulo;
	uint32_t dccg_ds_hw_cal_interval;
	uint32_t dccg_gate_disable_cntl;
	uint32_t dccg_gate_disable_cntl2;
	uint32_t dccg_gate_disable_cntl3;
	uint32_t dccg_gate_disable_cntl4;
	uint32_t dccg_gate_disable_cntl5;
	uint32_t dccg_gate_disable_cntl6;
	uint32_t dccg_global_fgcg_rep_cntl;
	uint32_t dccg_gtc_cntl;
	uint32_t dccg_gtc_current;
	uint32_t dccg_gtc_dto_incr;
	uint32_t dccg_gtc_dto_modulo;
	uint32_t dccg_perfmon_cntl;
	uint32_t dccg_perfmon_cntl2;
	uint32_t dccg_soft_reset;
	uint32_t dccg_test_clk_sel;
	uint32_t dccg_vsync_cnt_ctrl;
	uint32_t dccg_vsync_cnt_int_ctrl;
	uint32_t dccg_vsync_otg0_latch_value;
	uint32_t dccg_vsync_otg1_latch_value;
	uint32_t dccg_vsync_otg2_latch_value;
	uint32_t dccg_vsync_otg3_latch_value;
	uint32_t dccg_vsync_otg4_latch_value;
	uint32_t dccg_vsync_otg5_latch_value;
	uint32_t dispclk_cgtt_blk_ctrl_reg;
	uint32_t dispclk_freq_change_cntl;
	uint32_t dp_dto_dbuf_en;
	uint32_t dp_dto0_modulo;
	uint32_t dp_dto0_phase;
	uint32_t dp_dto1_modulo;
	uint32_t dp_dto1_phase;
	uint32_t dp_dto2_modulo;
	uint32_t dp_dto2_phase;
	uint32_t dp_dto3_modulo;
	uint32_t dp_dto3_phase;
	uint32_t dpiaclk_540m_dto_modulo;
	uint32_t dpiaclk_540m_dto_phase;
	uint32_t dpiaclk_810m_dto_modulo;
	uint32_t dpiaclk_810m_dto_phase;
	uint32_t dpiaclk_dto_cntl;
	uint32_t dpiasymclk_cntl;
	uint32_t dppclk_cgtt_blk_ctrl_reg;
	uint32_t dppclk_ctrl;
	uint32_t dppclk_dto_ctrl;
	uint32_t dppclk0_dto_param;
	uint32_t dppclk1_dto_param;
	uint32_t dppclk2_dto_param;
	uint32_t dppclk3_dto_param;
	uint32_t dprefclk_cgtt_blk_ctrl_reg;
	uint32_t dprefclk_cntl;
	uint32_t dpstreamclk_cntl;
	uint32_t dscclk_dto_ctrl;
	uint32_t dscclk0_dto_param;
	uint32_t dscclk1_dto_param;
	uint32_t dscclk2_dto_param;
	uint32_t dscclk3_dto_param;
	uint32_t dtbclk_dto_dbuf_en;
	uint32_t dtbclk_dto0_modulo;
	uint32_t dtbclk_dto0_phase;
	uint32_t dtbclk_dto1_modulo;

Annotation

Implementation Notes