drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h- Extension
.h- Size
- 17577 bytes
- Lines
- 531
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hw_shared.h
Detected Declarations
struct dc_biosstruct crtc_positionstruct dcp_gsl_paramsstruct gsl_paramsstruct drr_paramsstruct long_vtotal_paramsstruct vupdate_keepout_paramsstruct crtc_stereo_flagsstruct crc_paramsstruct dcn_otg_statestruct dcn_optc_reg_statestruct timing_generatorstruct dc_crtc_timingstruct drr_paramsstruct timing_generator_funcsenum crtc_stateenum crc_selectionenum otg_out_mux_destenum h_timing_div_modeenum timing_synchronization_typeenum crc_poly_mode
Annotated Snippet
struct crtc_position {
uint32_t vertical_count;
uint32_t horizontal_count;
uint32_t nominal_vcount;
};
struct dcp_gsl_params {
int gsl_group;
int gsl_master;
};
struct gsl_params {
int gsl0_en;
int gsl1_en;
int gsl2_en;
int gsl_master_en;
int gsl_master_mode;
int master_update_lock_gsl_en;
int gsl_window_start_x;
int gsl_window_end_x;
int gsl_window_start_y;
int gsl_window_end_y;
};
/* define the structure of Dynamic Refresh Mode */
struct drr_params {
uint32_t vertical_total_min;
uint32_t vertical_total_max;
uint32_t vertical_total_mid;
uint32_t vertical_total_mid_frame_num;
bool immediate_flip;
};
struct long_vtotal_params {
uint32_t vertical_total_min;
uint32_t vertical_total_max;
uint32_t vertical_blank_start;
};
#define LEFT_EYE_3D_PRIMARY_SURFACE 1
#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
enum crtc_state {
CRTC_STATE_VBLANK = 0,
CRTC_STATE_VACTIVE
};
struct vupdate_keepout_params {
int start_offset;
int end_offset;
int enable;
};
struct crtc_stereo_flags {
uint8_t PROGRAM_STEREO : 1;
uint8_t PROGRAM_POLARITY : 1;
uint8_t RIGHT_EYE_POLARITY : 1;
uint8_t FRAME_PACKED : 1;
uint8_t DISABLE_STEREO_DP_SYNC : 1;
};
enum crc_selection {
/* Order must match values expected by hardware */
UNION_WINDOW_A_B = 0,
UNION_WINDOW_A_NOT_B,
UNION_WINDOW_NOT_A_B,
UNION_WINDOW_NOT_A_NOT_B,
INTERSECT_WINDOW_A_B,
INTERSECT_WINDOW_A_NOT_B,
INTERSECT_WINDOW_NOT_A_B,
INTERSECT_WINDOW_NOT_A_NOT_B,
};
enum otg_out_mux_dest {
OUT_MUX_DIO = 0,
OUT_MUX_HPO_FRL = 1,
OUT_MUX_HPO_DP = 2,
};
enum h_timing_div_mode {
H_TIMING_NO_DIV,
H_TIMING_DIV_BY2,
H_TIMING_RESERVED,
H_TIMING_DIV_BY4,
};
enum timing_synchronization_type {
NOT_SYNCHRONIZABLE,
TIMING_SYNCHRONIZABLE,
VBLANK_SYNCHRONIZABLE
Annotation
- Immediate include surface: `hw_shared.h`.
- Detected declarations: `struct dc_bios`, `struct crtc_position`, `struct dcp_gsl_params`, `struct gsl_params`, `struct drr_params`, `struct long_vtotal_params`, `struct vupdate_keepout_params`, `struct crtc_stereo_flags`, `struct crc_params`, `struct dcn_otg_state`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.