drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h- Extension
.h- Size
- 4361 bytes
- Lines
- 121
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
core_types.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef DC_INC_LINK_ENC_CFG_H_
#define DC_INC_LINK_ENC_CFG_H_
/* This module implements functionality for dynamically assigning DIG link
* encoder resources to display endpoints (links).
*/
#include "core_types.h"
/*
* Initialise link encoder resource tracking.
*/
void link_enc_cfg_init(
const struct dc *dc,
struct dc_state *state);
/*
* Copies a link encoder assignment from another state.
*/
void link_enc_cfg_copy(const struct dc_state *src_ctx, struct dc_state *dst_ctx);
/*
* Algorithm for assigning available DIG link encoders to streams.
*
* Update link_enc_assignments table and link_enc_avail list accordingly in
* struct resource_context.
*
* Loop over all streams twice:
* a) First assign encoders to unmappable endpoints.
* b) Then assign encoders to mappable endpoints.
*/
void link_enc_cfg_link_encs_assign(
struct dc *dc,
struct dc_state *state,
struct dc_stream_state *streams[],
uint8_t stream_count);
/*
* Unassign a link encoder from a stream.
*
* Update link_enc_assignments table and link_enc_avail list accordingly in
* struct resource_context.
*/
void link_enc_cfg_link_enc_unassign(
struct dc_state *state,
struct dc_stream_state *stream);
/*
* Check whether the transmitter driven by a link encoder is a mappable
* endpoint.
*/
bool link_enc_cfg_is_transmitter_mappable(
struct dc *dc,
struct link_encoder *link_enc);
/* Return stream using DIG link encoder resource. NULL if unused. */
struct dc_stream_state *link_enc_cfg_get_stream_using_link_enc(
struct dc *dc,
enum engine_id eng_id);
/* Return link using DIG link encoder resource. NULL if unused. */
struct dc_link *link_enc_cfg_get_link_using_link_enc(
struct dc *dc,
enum engine_id eng_id);
/* Return DIG link encoder used by link. NULL if unused. */
struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
struct dc *dc,
const struct dc_link *link);
/* Return next available DIG link encoder. NULL if none available. */
struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc);
/* Return DIG link encoder. NULL if unused. */
struct link_encoder *link_enc_cfg_get_link_enc(const struct dc_link *link);
/* Return DIG link encoder used by stream in current/previous state. NULL if unused. */
struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream_current(
struct dc *dc,
const struct dc_stream_state *stream);
/* Return true if encoder available to use. */
bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);
/* Returns true if encoder assignments in supplied state pass validity checks. */
bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
/* Set the link encoder assignment mode for the current_state to LINK_ENC_CFG_TRANSIENT mode.
* This indicates that a new_state is in the process of being applied to hardware.
* During this transition, old and new encoder assignments should be accessible from the old_state.
Annotation
- Immediate include surface: `core_types.h`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.