drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
Extension
.c
Size
39588 bytes
Lines
1307
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (link->dpcd_caps.branch_dev_id) {
		case DP_BRANCH_DEVICE_ID_0022B9:
			/* alternate scrambler reset is required for Travis
			 * for the case when external chip does not
			 * provide sink device id, alternate scrambler
			 * scheme will  be overriden later by querying
			 * Encoder features
			 */
			if (strncmp(
				link->dpcd_caps.branch_dev_name,
				DP_VGA_LVDS_CONVERTER_ID_2,
				sizeof(
				link->dpcd_caps.
				branch_dev_name)) == 0) {
					return DP_PANEL_MODE_SPECIAL;
			}
			break;
		case DP_BRANCH_DEVICE_ID_00001A:
			/* alternate scrambler reset is required for NUTMEG
			 * for the case when external chip does not provide
			 * sink device id, alternate scrambler scheme will
			 * be overriden later by querying Encoder feature
			 */
			if (strncmp(link->dpcd_caps.branch_dev_name,
				DP_VGA_LVDS_CONVERTER_ID_3,
				sizeof(
				link->dpcd_caps.
				branch_dev_name)) == 0) {
					return DP_PANEL_MODE_SPECIAL;
			}
			break;
		default:
			break;
		}
	}

	if (link->dpcd_caps.panel_mode_edp &&
		(link->connector_signal == SIGNAL_TYPE_EDP ||
		 (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
		  link->is_internal_display))) {
		return DP_PANEL_MODE_EDP;
	}

	return DP_PANEL_MODE_DEFAULT;
}

bool edp_set_backlight_level_nits(struct dc_link *link,
		bool isHDR,
		uint32_t backlight_millinits,
		uint32_t transition_time_in_ms)
{
	if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
			link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
		return false;

	if (link->is_dds && !link->dpcd_caps.panel_luminance_control)
		return true;

	// use internal backlight control if dmub capabilities are not present
	if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &&
		!link->dc->caps.dmub_caps.aux_backlight_support) {
		uint8_t backlight_enable = 0;
		struct target_luminance_value *target_luminance = NULL;

		//if target luminance value is greater than 24 bits, clip the value to 24 bits
		if (backlight_millinits > 0xFFFFFF)
			backlight_millinits = 0xFFFFFF;

		target_luminance = (struct target_luminance_value *)&backlight_millinits;

		//make sure we disable AMD ABC first.
		core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
			&backlight_enable, sizeof(uint8_t));
		if (backlight_enable) {
			backlight_enable = 0;
			core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
					&backlight_enable, 1);
		}

		core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
			&backlight_enable, sizeof(uint8_t));

		backlight_enable |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;

		if (core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
			&backlight_enable,
			sizeof(backlight_enable)) != DC_OK)
			return false;

		if (core_link_write_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,

Annotation

Implementation Notes