drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
Extension: .h
Size: 11689 bytes
Lines: 212
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dcn20/dcn20_mmhubbub.h
dcn30/dcn30_mmhubbub.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DC_MCIF_WB_DCN32_H__
#define __DC_MCIF_WB_DCN32_H__

#include "dcn20/dcn20_mmhubbub.h"
#include "dcn30/dcn30_mmhubbub.h"

#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \
	SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
	SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
	SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
	SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
	SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
	SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
	SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
	SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
	SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
	SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
	SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
	SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
	SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
	SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)


#define MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\

Annotation

Immediate include surface: `dcn20/dcn20_mmhubbub.h`, `dcn30/dcn30_mmhubbub.h`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.