drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
Extension
.c
Size
38959 bytes
Lines
1053
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
			}
		}
		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
		}
	}
}

void mpc32_power_on_blnd_lut(
	struct mpc *mpc,
	uint32_t mpcc_id,
	bool power_on)
{
	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);

	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
		if (power_on) {
			REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
			REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
		} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
			/* TODO: change to mpc
			 *  dpp_base->ctx->dc->optimized_required = true;
			 *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
			 */
		}
	} else {
		REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
				MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
	}
}

static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
{
	enum dc_lut_mode mode;
	uint32_t mode_current = 0;
	uint32_t in_use = 0;

	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

	REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
			MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
	REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
			MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);

	switch (mode_current) {
	case 0:
	case 1:
		mode = LUT_BYPASS;
		break;

	case 2:
		if (in_use == 0)
			mode = LUT_RAM_A;
		else
			mode = LUT_RAM_B;
		break;
	default:
		mode = LUT_BYPASS;
		break;
	}
	return mode;
}

void mpc32_configure_post1dlut(
		struct mpc *mpc,
		uint32_t mpcc_id,
		bool is_ram_a)
{
	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

	//TODO: this
	REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
			MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
			MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);

	REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
}

static void mpc32_post1dlut_get_reg_field(
		struct dcn30_mpc *mpc,
		struct dcn3_xfer_func_reg *reg)
{

Annotation

Implementation Notes