drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
Extension
.c
Size
20382 bytes
Lines
647
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (is_17x17x17) {
			lut0 = lut3d->tetrahedral_17.lut0;
			lut1 = lut3d->tetrahedral_17.lut1;
			lut2 = lut3d->tetrahedral_17.lut2;
			lut3 = lut3d->tetrahedral_17.lut3;
			lut_size0 = sizeof(lut3d->tetrahedral_17.lut0)/
						sizeof(lut3d->tetrahedral_17.lut0[0]);
			lut_size  = sizeof(lut3d->tetrahedral_17.lut1)/
						sizeof(lut3d->tetrahedral_17.lut1[0]);
		} else {
			lut0 = lut3d->tetrahedral_9.lut0;
			lut1 = lut3d->tetrahedral_9.lut1;
			lut2 = lut3d->tetrahedral_9.lut2;
			lut3 = lut3d->tetrahedral_9.lut3;
			lut_size0 = sizeof(lut3d->tetrahedral_9.lut0)/
					sizeof(lut3d->tetrahedral_9.lut0[0]);
			lut_size  = sizeof(lut3d->tetrahedral_9.lut1)/
					sizeof(lut3d->tetrahedral_9.lut1[0]);
			}

		mpc32_select_3dlut_ram(mpc, next_mode,
					is_12bits_color_channel, mpcc_id);
		mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
		if (is_12bits_color_channel)
			mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
		else
			mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);

		mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
		if (is_12bits_color_channel)
			mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
		else
			mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);

		mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
		if (is_12bits_color_channel)
			mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
		else
			mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);

		mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
		if (is_12bits_color_channel)
			mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
		else
			mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);

		if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
			mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

		break;
	}

}

void mpc401_program_lut_mode(
		struct mpc *mpc,
		const enum MCM_LUT_ID id,
		const enum MCM_LUT_XABLE xable,
		bool lut_bank_a,
		int mpcc_id)
{
	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

	switch (id) {
	case MCM_LUT_3DLUT:
		switch (xable) {
		case MCM_LUT_DISABLE:
			REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0);
			break;
		case MCM_LUT_ENABLE:
			REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2);
			break;
		}
		break;
	case MCM_LUT_SHAPER:
		switch (xable) {
		case MCM_LUT_DISABLE:
			REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0);
			break;
		case MCM_LUT_ENABLE:
			REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2);
			break;
		}
		break;
	case MCM_LUT_1DLUT:
		switch (xable) {
		case MCM_LUT_DISABLE:
			REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
					MPCC_MCM_1DLUT_MODE, 0);
			break;

Annotation

Implementation Notes