drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
Extension
.c
Size
42972 bytes
Lines
1122
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.

#include "reg_helper.h"
#include "dc.h"
#include "dcn42_mpc.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
#include "mpc.h"

#define REG(reg)\
	mpc42->mpc_regs->reg

#define CTX \
	mpc42->base.ctx

#undef FN
#define FN(reg_name, field_name) \
	mpc42->mpc_shift->field_name, mpc42->mpc_mask->field_name


void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
{
	mpcc->mpcc_id = mpcc_inst;
	mpcc->dpp_id = 0xf;
	mpcc->mpcc_bot = NULL;
	mpcc->blnd_cfg.overlap_only = false;
	mpcc->blnd_cfg.global_alpha = 0xfff;
	mpcc->blnd_cfg.global_gain = 0xfff;
	mpcc->blnd_cfg.background_color_bpc = 4;
	mpcc->blnd_cfg.bottom_gain_mode = 0;
	mpcc->blnd_cfg.top_gain = 0x1f000;
	mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
	mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
	mpcc->sm_cfg.enable = false;
	mpcc->shared_bottom = false;
}

void mpc42_update_blending(
	struct mpc *mpc,
	struct mpcc_blnd_cfg *blnd_cfg,
	int mpcc_id)
{
	struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);

	struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

	REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
			MPCC_ALPHA_BLND_MODE,		blnd_cfg->alpha_mode,
			MPCC_ALPHA_MULTIPLIED_MODE,	blnd_cfg->pre_multiplied_alpha,
			MPCC_BLND_ACTIVE_OVERLAP_ONLY,	blnd_cfg->overlap_only,
			MPCC_BG_BPC,			blnd_cfg->background_color_bpc,
			MPCC_BOT_GAIN_MODE,		blnd_cfg->bottom_gain_mode);
	REG_UPDATE_2(MPCC_CONTROL2[mpcc_id],
			MPCC_GLOBAL_ALPHA,		blnd_cfg->global_alpha,
			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain);

	REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
	REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
	REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);

	mpcc->blnd_cfg = *blnd_cfg;
}

/* Shaper functions */
void mpc42_power_on_shaper_3dlut(
	struct mpc *mpc,
	uint32_t mpcc_id,
	bool power_on)
{
	uint32_t power_status_shaper = 2;
	uint32_t power_status_3dlut  = 2;
	struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc);
	int max_retries = 10;

	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
		MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
		MPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1:0);
	/* wait for memory to fully power up */
	if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
	}

	/*read status is not mandatory, it is just for debugging*/
	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);

Annotation

Implementation Notes