drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
Extension
.c
Size
18905 bytes
Lines
655
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (pipe_ctx) {
			if (pipe_ctx->stream)
				all_stream_disabled = false;
		}

		if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])
			all_mpcc_disabled = false;

		if (pg_cntl->pg_pipe_res_enable[PG_OPP][i])
			all_opp_disabled = false;

		if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i])
			all_optc_disabled = false;
	}

	if (!power_on) {
		if (!all_mpcc_disabled || !all_opp_disabled || !all_optc_disabled
			|| !all_stream_disabled)
			return;
	}

	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
	if (org_ip_request_cntl == 0)
		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

	/* MPC, OPP, OPTC, DWB */
	REG_UPDATE(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);
	REG_WAIT(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);

	for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
		pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;
		pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on;
		pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on;
	}
}


void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl)
{
	unsigned int i = 0;
	bool block_enabled;

	pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl);

	block_enabled = pg_cntl42_io_clk_status(pg_cntl);
	pg_cntl->pg_res_enable[PG_DCCG] = block_enabled;
	pg_cntl->pg_res_enable[PG_DCIO] = block_enabled;
	pg_cntl->pg_res_enable[PG_DCOH] = block_enabled;

	block_enabled = pg_cntl42_dio_pg_status(pg_cntl);
	pg_cntl->pg_res_enable[PG_DIO] = block_enabled;

	block_enabled = pg_cntl42_mem_status(pg_cntl);
	pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled;
	pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled;

	for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
		block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, i);
		pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled;
		pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled;

		block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, i);
		pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled;
	}

	block_enabled = pg_cntl42_plane_otg_status(pg_cntl);
	for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
		pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;
		pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled;
		pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled;
	}
}

static const struct pg_cntl_funcs pg_cntl42_funcs = {
	.init_pg_status = pg_cntl42_init_pg_status,
	.dsc_pg_control = pg_cntl42_dsc_pg_control,
	.hubp_dpp_pg_control = pg_cntl42_hubp_dpp_pg_control,
	.hpo_pg_control = pg_cntl42_hpo_pg_control,
	.io_clk_pg_control = pg_cntl42_io_clk_pg_control,
	.plane_otg_pg_control = pg_cntl42_plane_otg_pg_control,
	.mpcc_pg_control = pg_cntl42_mpcc_pg_control,
	.opp_pg_control = pg_cntl42_opp_pg_control,
	.optc_pg_control = pg_cntl42_optc_pg_control,
	.mem_pg_control = pg_cntl42_mem_pg_control,
	.dio_pg_control = pg_cntl42_dio_pg_control
};

struct pg_cntl *pg_cntl42_create(
	struct dc_context *ctx,
	const struct pg_cntl_registers *regs,

Annotation

Implementation Notes