drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c- Extension
.c- Size
- 38586 bytes
- Lines
- 1506
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hdce/dce_6_0_d.hdce/dce_6_0_sh_mask.hdm_services.hlink_encoder.hstream_encoder.hresource.hclk_mgr.hinclude/irq_service_interface.hirq/dce60/irq_service_dce60.hdce110/dce110_timing_generator.hdce110/dce110_resource.hdce60/dce60_timing_generator.hdce/dce_mem_input.hdce/dce_link_encoder.hdce/dce_stream_encoder.hdce/dce_ipp.hdce/dce_transform.hdce/dce_opp.hdce/dce_clock_source.hdce/dce_audio.hdce/dce_hwseq.hdce60/dce60_hwseq.hdce100/dce100_resource.hdce/dce_panel_cntl.hreg_helper.hdce/dce_dmcu.hdce/dce_aux.hdce/dce_abm.hdce/dce_i2c.hdce60_resource.hgmc/gmc_6_0_d.h
Detected Declarations
function map_transmitter_id_to_phy_instancefunction read_dce_strapsfunction dce60_transform_destroyfunction dce60_clock_source_destroyfunction dce60_resource_destructfunction dce60_destroy_resource_poolfunction dce60_constructfunction dce61_constructfunction dce64_construct
Annotated Snippet
if (pool->base.mis[i] != NULL) {
kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
if (pool->base.timing_generators[i] != NULL) {
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
kfree(pool->base.hw_i2cs[i]);
pool->base.hw_i2cs[i] = NULL;
}
if (pool->base.sw_i2cs[i] != NULL) {
kfree(pool->base.sw_i2cs[i]);
pool->base.sw_i2cs[i] = NULL;
}
}
for (i = 0; i < pool->base.stream_enc_count; i++) {
if (pool->base.stream_enc[i] != NULL)
kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
}
for (i = 0; i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] != NULL) {
dce60_clock_source_destroy(&pool->base.clock_sources[i]);
}
}
if (pool->base.abm != NULL)
dce_abm_destroy(&pool->base.abm);
if (pool->base.dmcu != NULL)
dce_dmcu_destroy(&pool->base.dmcu);
if (pool->base.dp_clock_source != NULL)
dce60_clock_source_destroy(&pool->base.dp_clock_source);
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i] != NULL) {
dce_aud_destroy(&pool->base.audios[i]);
}
}
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
}
static void dce60_destroy_resource_pool(struct resource_pool **pool)
{
struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
dce60_resource_destruct(dce110_pool);
kfree(dce110_pool);
*pool = NULL;
}
static const struct resource_funcs dce60_res_pool_funcs = {
.destroy = dce60_destroy_resource_pool,
.link_enc_create = dce60_link_encoder_create,
.panel_cntl_create = dce60_panel_cntl_create,
.validate_bandwidth = dce100_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,
.validate_global = dce100_validate_global,
.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
};
static bool dce60_construct(
uint8_t num_virtual_links,
struct dc *dc,
struct dce110_resource_pool *pool)
{
unsigned int i;
struct dc_context *ctx = dc->ctx;
struct dc_bios *bp;
ctx->dc_bios->regs = &bios_regs;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce60_res_pool_funcs;
Annotation
- Immediate include surface: `linux/slab.h`, `dce/dce_6_0_d.h`, `dce/dce_6_0_sh_mask.h`, `dm_services.h`, `link_encoder.h`, `stream_encoder.h`, `resource.h`, `clk_mgr.h`.
- Detected declarations: `function map_transmitter_id_to_phy_instance`, `function read_dce_straps`, `function dce60_transform_destroy`, `function dce60_clock_source_destroy`, `function dce60_resource_destruct`, `function dce60_destroy_resource_pool`, `function dce60_construct`, `function dce61_construct`, `function dce64_construct`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.