drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c- Extension
.c- Size
- 78629 bytes
- Lines
- 2841
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hdc.hdcn20/dcn20_init.hresource.hinclude/irq_service_interface.hdcn20/dcn20_resource.hdml/dcn20/dcn20_fpu.hdcn10/dcn10_hubp.hdcn10/dcn10_ipp.hdcn20/dcn20_hubbub.hdcn20/dcn20_mpc.hdcn20/dcn20_hubp.hirq/dcn20/irq_service_dcn20.hdcn20/dcn20_dpp.hdcn20/dcn20_optc.hdcn20/dcn20_hwseq.hdce110/dce110_hwseq.hdcn10/dcn10_resource.hdcn20/dcn20_opp.hdcn20/dcn20_dsc.hdcn20/dcn20_link_encoder.hdcn20/dcn20_stream_encoder.hdce/dce_clock_source.hdce/dce_audio.hdce/dce_hwseq.hdio/virtual/virtual_stream_encoder.hdce110/dce110_resource.hdml/display_mode_vba.hdcn20/dcn20_dccg.hdcn20/dcn20_vmid.hdce/dce_panel_cntl.hdcn20/dcn20_dwb.h
Detected Declarations
enum dcn20_clk_src_array_idfunction map_transmitter_id_to_phy_instancefunction dcn20_dpp_destroyfunction read_dce_strapsfunction dcn20_clock_source_destroyfunction dcn20_dsc_destroyfunction dcn20_resource_destructfunction get_pixel_clock_parametersfunction build_clamping_paramsfunction dcn20_build_pipe_pix_clk_paramsfunction build_pipe_hw_paramfunction dcn20_build_mapped_resourcefunction dcn20_acquire_dscfunction dcn20_release_dscfunction dcn20_add_dsc_to_stream_resourcefunction remove_dsc_from_stream_resourcefunction dcn20_add_stream_to_ctxfunction dcn20_remove_stream_from_ctxfunction dcn20_split_stream_for_odmfunction dcn20_split_stream_for_mpcfunction dcn20_calc_max_scaled_timefunction dcn20_set_mcif_arb_paramsfunction dcn20_validate_dscfunction availablefunction dcn20_merge_pipes_for_validatefunction is_dual_planefunction dcn20_validate_apply_pipe_split_flagsfunction dcn20_fast_validate_bwfunction dcn20_validate_bandwidthfunction dcn20_get_dcc_compression_capfunction dcn20_destroy_resource_poolfunction dcn20_patch_unknown_plane_statefunction dcn20_release_pipefunction dcn20_dwbc_createfunction dcn20_mmhubbub_createfunction dcn20_pp_smu_destroyfunction get_dml_project_versionfunction init_soc_bounding_boxfunction dcn20_resource_construct
Annotated Snippet
if (pool->base.stream_enc[i] != NULL) {
kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
pool->base.stream_enc[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
if (pool->base.mpc != NULL) {
kfree(TO_DCN20_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
if (pool->base.hubbub != NULL) {
kfree(pool->base.hubbub);
pool->base.hubbub = NULL;
}
if (pool->base.dio != NULL) {
kfree(TO_DCN10_DIO(pool->base.dio));
pool->base.dio = NULL;
}
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.dpps[i] != NULL)
dcn20_dpp_destroy(&pool->base.dpps[i]);
if (pool->base.ipps[i] != NULL)
pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
if (pool->base.hubps[i] != NULL) {
kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
pool->base.hubps[i] = NULL;
}
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
kfree(pool->base.hw_i2cs[i]);
pool->base.hw_i2cs[i] = NULL;
}
if (pool->base.sw_i2cs[i] != NULL) {
kfree(pool->base.sw_i2cs[i]);
pool->base.sw_i2cs[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
if (pool->base.mcif_wb[i] != NULL) {
kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
pool->base.mcif_wb[i] = NULL;
}
}
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(&pool->base.audios[i]);
}
for (i = 0; i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] != NULL) {
dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
pool->base.clock_sources[i] = NULL;
}
}
Annotation
- Immediate include surface: `dm_services.h`, `dc.h`, `dcn20/dcn20_init.h`, `resource.h`, `include/irq_service_interface.h`, `dcn20/dcn20_resource.h`, `dml/dcn20/dcn20_fpu.h`, `dcn10/dcn10_hubp.h`.
- Detected declarations: `enum dcn20_clk_src_array_id`, `function map_transmitter_id_to_phy_instance`, `function dcn20_dpp_destroy`, `function read_dce_straps`, `function dcn20_clock_source_destroy`, `function dcn20_dsc_destroy`, `function dcn20_resource_destruct`, `function get_pixel_clock_parameters`, `function build_clamping_params`, `function dcn20_build_pipe_pix_clk_params`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.