drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
Extension
.h
Size
6099 bytes
Lines
172
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn20_resource_pool {
	struct resource_pool base;
};
struct resource_pool *dcn20_create_resource_pool(
		const struct dc_init_data *init_data,
		struct dc *dc);

struct link_encoder *dcn20_link_encoder_create(
	struct dc_context *ctx,
	const struct encoder_init_data *enc_init_data);

unsigned int dcn20_calc_max_scaled_time(
		unsigned int time_per_pixel,
		enum mmhubbub_wbif_mode mode,
		unsigned int urgent_watermark);

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
		const struct dc_state *cur_ctx,
		struct dc_state *new_ctx,
		const struct resource_pool *pool,
		const struct pipe_ctx *opp_head_pipe);
void dcn20_release_pipe(struct dc_state *context,
			struct pipe_ctx *pipe,
			const struct resource_pool *pool);
struct stream_encoder *dcn20_stream_encoder_create(
	enum engine_id eng_id,
	struct dc_context *ctx);

struct dce_hwseq *dcn20_hwseq_create(
	struct dc_context *ctx);

bool dcn20_get_dcc_compression_cap(const struct dc *dc,
		const struct dc_dcc_surface_param *input,
		struct dc_surface_dcc_cap *output);

void dcn20_dpp_destroy(struct dpp **dpp);

struct dpp *dcn20_dpp_create(
	struct dc_context *ctx,
	uint32_t inst);

struct input_pixel_processor *dcn20_ipp_create(
	struct dc_context *ctx, uint32_t inst);

struct output_pixel_processor *dcn20_opp_create(
	struct dc_context *ctx, uint32_t inst);

struct dce_aux *dcn20_aux_engine_create(
	struct dc_context *ctx, uint32_t inst);

struct dce_i2c_hw *dcn20_i2c_hw_create(
	struct dc_context *ctx,
	uint32_t inst);

void dcn20_clock_source_destroy(struct clock_source **clk_src);

struct display_stream_compressor *dcn20_dsc_create(
	struct dc_context *ctx, uint32_t inst);
void dcn20_dsc_destroy(struct display_stream_compressor **dsc);

struct hubp *dcn20_hubp_create(
	struct dc_context *ctx,
	uint32_t inst);
struct timing_generator *dcn20_timing_generator_create(
		struct dc_context *ctx,
		uint32_t instance);
struct mpc *dcn20_mpc_create(struct dc_context *ctx);
struct hubbub *dcn20_hubbub_create(struct dc_context *ctx);

bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);

void dcn20_set_mcif_arb_params(
		struct dc *dc,
		struct dc_state *context,
		display_e2e_pipe_params_st *pipes,
		int pipe_cnt);
enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);
void dcn20_merge_pipes_for_validate(
		struct dc *dc,
		struct dc_state *context);
int dcn20_validate_apply_pipe_split_flags(
		struct dc *dc,
		struct dc_state *context,
		int vlevel,
		int *split,
		bool *merge);
void dcn20_release_dsc(struct resource_context *res_ctx,
			const struct resource_pool *pool,
			struct display_stream_compressor **dsc);

Annotation

Implementation Notes