drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c- Extension
.c- Size
- 34708 bytes
- Lines
- 1361
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hdc.hdcn201/dcn201_init.hdml/dcn20/dcn20_fpu.hresource.hinclude/irq_service_interface.hdcn201_resource.hdcn20/dcn20_resource.hdcn10/dcn10_hubp.hdcn10/dcn10_ipp.hdcn201/dcn201_mpc.hdcn201/dcn201_hubp.hirq/dcn201/irq_service_dcn201.hdcn201/dcn201_dpp.hdcn201/dcn201_hubbub.hdcn201/dcn201_dccg.hdcn201/dcn201_optc.hdcn201/dcn201_hwseq.hdce110/dce110_hwseq.hdcn201/dcn201_opp.hdcn201/dcn201_link_encoder.hdcn20/dcn20_stream_encoder.hdce/dce_clock_source.hdce/dce_audio.hdce/dce_hwseq.hdio/virtual/virtual_stream_encoder.hdce110/dce110_resource.hdce/dce_aux.hdce/dce_i2c.hdcn10/dcn10_resource.hdio/dcn10/dcn10_dio.hcyan_skillfish_ip_offset.h
Detected Declarations
enum dcn20_clk_src_array_idfunction dcn201_dpp_destroyfunction read_dce_strapsfunction dcn201_clock_source_destroyfunction dcn201_resource_destructfunction dcn201_get_dcc_compression_capfunction dcn201_populate_dml_writeback_from_contextfunction dcn201_destroy_resource_poolfunction dcn201_link_initfunction dcn201_resource_construct
Annotated Snippet
if (pool->base.stream_enc[i] != NULL) {
kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
pool->base.stream_enc[i] = NULL;
}
}
if (pool->base.mpc != NULL) {
kfree(TO_DCN201_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
if (pool->base.hubbub != NULL) {
kfree(pool->base.hubbub);
pool->base.hubbub = NULL;
}
if (pool->base.dio != NULL) {
kfree(TO_DCN10_DIO(pool->base.dio));
pool->base.dio = NULL;
}
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.dpps[i] != NULL)
dcn201_dpp_destroy(&pool->base.dpps[i]);
if (pool->base.ipps[i] != NULL)
pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
if (pool->base.hubps[i] != NULL) {
kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
pool->base.hubps[i] = NULL;
}
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
}
for (i = 0; i < pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(&pool->base.audios[i]);
}
for (i = 0; i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] != NULL) {
dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
pool->base.clock_sources[i] = NULL;
}
}
if (pool->base.dp_clock_source != NULL) {
dcn201_clock_source_destroy(&pool->base.dp_clock_source);
pool->base.dp_clock_source = NULL;
}
if (pool->base.dccg != NULL)
dcn_dccg_destroy(&pool->base.dccg);
}
static struct hubp *dcn201_hubp_create(
struct dc_context *ctx,
uint32_t inst)
{
struct dcn201_hubp *hubp201 =
kzalloc_obj(struct dcn201_hubp);
if (!hubp201)
return NULL;
if (dcn201_hubp_construct(hubp201, ctx, inst,
&hubp_regs[inst], &hubp_shift, &hubp_mask))
return &hubp201->base;
kfree(hubp201);
return NULL;
}
static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(
Annotation
- Immediate include surface: `dm_services.h`, `dc.h`, `dcn201/dcn201_init.h`, `dml/dcn20/dcn20_fpu.h`, `resource.h`, `include/irq_service_interface.h`, `dcn201_resource.h`, `dcn20/dcn20_resource.h`.
- Detected declarations: `enum dcn20_clk_src_array_id`, `function dcn201_dpp_destroy`, `function read_dce_straps`, `function dcn201_clock_source_destroy`, `function dcn201_resource_destruct`, `function dcn201_get_dcc_compression_cap`, `function dcn201_populate_dml_writeback_from_context`, `function dcn201_destroy_resource_pool`, `function dcn201_link_init`, `function dcn201_resource_construct`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.