drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c- Extension
.c- Size
- 43916 bytes
- Lines
- 1769
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hdm_services.hdc.hdcn21/dcn21_init.hresource.hinclude/irq_service_interface.hdcn20/dcn20_resource.hdcn21/dcn21_resource.hdml/dcn20/dcn20_fpu.hclk_mgr.hdcn10/dcn10_hubp.hdcn10/dcn10_ipp.hdcn20/dcn20_hubbub.hdcn20/dcn20_mpc.hdcn20/dcn20_hubp.hdcn21/dcn21_hubp.hirq/dcn21/irq_service_dcn21.hdcn20/dcn20_dpp.hdcn20/dcn20_optc.hdcn21/dcn21_hwseq.hdce110/dce110_hwseq.hdcn20/dcn20_opp.hdcn20/dcn20_dsc.hdcn21/dcn21_link_encoder.hdcn20/dcn20_stream_encoder.hdce/dce_clock_source.hdce/dce_audio.hdce/dce_hwseq.hdio/virtual/virtual_stream_encoder.hdml/display_mode_vba.hdcn20/dcn20_dccg.hdcn21/dcn21_dccg.h
Detected Declarations
enum dcn20_clk_src_array_idfunction dcn21_resource_destructfunction dcn21_fast_validate_bwfunction DC_FP_STARTfunction dcn21_destroy_resource_poolfunction read_dce_strapsfunction dcn21_pp_smu_destroyfunction map_transmitter_id_to_phy_instancefunction dcn21_get_panel_config_defaultsfunction read_pipe_fusesfunction dcn21_patch_unknown_plane_statefunction dcn21_update_bw_bounding_boxfunction dcn21_resource_construct
Annotated Snippet
if (pool->base.stream_enc[i] != NULL) {
kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
pool->base.stream_enc[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
if (pool->base.mpc != NULL) {
kfree(TO_DCN20_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
if (pool->base.hubbub != NULL) {
kfree(pool->base.hubbub);
pool->base.hubbub = NULL;
}
if (pool->base.dio != NULL) {
kfree(TO_DCN10_DIO(pool->base.dio));
pool->base.dio = NULL;
}
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.dpps[i] != NULL)
dcn20_dpp_destroy(&pool->base.dpps[i]);
if (pool->base.ipps[i] != NULL)
pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
if (pool->base.hubps[i] != NULL) {
kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
pool->base.hubps[i] = NULL;
}
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
kfree(pool->base.hw_i2cs[i]);
pool->base.hw_i2cs[i] = NULL;
}
if (pool->base.sw_i2cs[i] != NULL) {
kfree(pool->base.sw_i2cs[i]);
pool->base.sw_i2cs[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
if (pool->base.mcif_wb[i] != NULL) {
kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
pool->base.mcif_wb[i] = NULL;
}
}
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(&pool->base.audios[i]);
}
for (i = 0; i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] != NULL) {
dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
pool->base.clock_sources[i] = NULL;
}
}
if (pool->base.dp_clock_source != NULL) {
Annotation
- Immediate include surface: `linux/slab.h`, `dm_services.h`, `dc.h`, `dcn21/dcn21_init.h`, `resource.h`, `include/irq_service_interface.h`, `dcn20/dcn20_resource.h`, `dcn21/dcn21_resource.h`.
- Detected declarations: `enum dcn20_clk_src_array_id`, `function dcn21_resource_destruct`, `function dcn21_fast_validate_bw`, `function DC_FP_START`, `function dcn21_destroy_resource_pool`, `function read_dce_straps`, `function dcn21_pp_smu_destroy`, `function map_transmitter_id_to_phy_instance`, `function dcn21_get_panel_config_defaults`, `function read_pipe_fuses`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.