drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

Extension

.h

Size

1567 bytes

Lines

39

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• core_types.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _DCN302_RESOURCE_H_
#define _DCN302_RESOURCE_H_

#include "core_types.h"

extern struct _vcs_dpi_ip_params_st dcn3_02_ip;
extern struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc;

struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);

void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

#endif /* _DCN302_RESOURCE_H_ */

Annotation

• Immediate include surface: `core_types.h`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.