drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c- Extension
.c- Size
- 65702 bytes
- Lines
- 2359
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hdc.hdcn31/dcn31_init.hresource.hinclude/irq_service_interface.hdcn315_resource.hdcn20/dcn20_resource.hdcn30/dcn30_resource.hdcn31/dcn31_resource.hdcn10/dcn10_ipp.hdcn30/dcn30_hubbub.hdcn31/dcn31_hubbub.hdcn30/dcn30_mpc.hdcn31/dcn31_hubp.hirq/dcn315/irq_service_dcn315.hdcn30/dcn30_dpp.hdcn31/dcn31_optc.hdcn20/dcn20_hwseq.hdcn30/dcn30_hwseq.hdce110/dce110_hwseq.hdcn30/dcn30_opp.hdcn20/dcn20_dsc.hdcn30/dcn30_vpg.hdcn30/dcn30_afmt.hdcn30/dcn30_dio_stream_encoder.hdcn30/dcn30_hpo_frl_stream_encoder.hdcn30/dcn30_hpo_frl_link_encoder.hdcn31/dcn31_hpo_dp_stream_encoder.hdcn31/dcn31_hpo_dp_link_encoder.hdcn31/dcn31_apg.hdcn31/dcn31_dio_link_encoder.hdcn31/dcn31_vpg.h
Detected Declarations
enum dcn31_clk_src_array_idfunction dcn31_dpp_destroyfunction read_dce_strapsfunction dcn315_resource_destructfunction dcn31_dwbc_createfunction dcn31_mmhubbub_createfunction dcn315_destroy_resource_poolfunction is_dual_planefunction source_format_to_bppfunction allow_pixel_rate_crbfunction dcn315_populate_dml_pipes_from_contextfunction dcn315_get_panel_config_defaultsfunction dcn315_get_power_profilefunction dcn315_update_bw_bounding_boxfunction dcn315_resource_construct
Annotated Snippet
if (pool->base.stream_enc[i] != NULL) {
if (pool->base.stream_enc[i]->vpg != NULL) {
kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
pool->base.stream_enc[i]->vpg = NULL;
}
if (pool->base.stream_enc[i]->afmt != NULL) {
kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
pool->base.stream_enc[i]->afmt = NULL;
}
kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
pool->base.stream_enc[i] = NULL;
}
}
for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
if (pool->base.hpo_frl_stream_enc[i] != NULL) {
if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
}
if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
}
kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
pool->base.hpo_frl_stream_enc[i] = NULL;
}
}
for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
if (pool->base.hpo_dp_stream_enc[i] != NULL) {
if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
}
if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
pool->base.hpo_dp_stream_enc[i]->apg = NULL;
}
kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
pool->base.hpo_dp_stream_enc[i] = NULL;
}
}
for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
if (pool->base.hpo_dp_link_enc[i] != NULL) {
kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
pool->base.hpo_dp_link_enc[i] = NULL;
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
if (pool->base.mpc != NULL) {
kfree(TO_DCN20_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
if (pool->base.hubbub != NULL) {
kfree(pool->base.hubbub);
pool->base.hubbub = NULL;
}
if (pool->base.dio != NULL) {
kfree(TO_DCN10_DIO(pool->base.dio));
pool->base.dio = NULL;
}
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.dpps[i] != NULL)
dcn31_dpp_destroy(&pool->base.dpps[i]);
if (pool->base.ipps[i] != NULL)
pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
if (pool->base.hubps[i] != NULL) {
kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
pool->base.hubps[i] = NULL;
}
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
}
for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
Annotation
- Immediate include surface: `dm_services.h`, `dc.h`, `dcn31/dcn31_init.h`, `resource.h`, `include/irq_service_interface.h`, `dcn315_resource.h`, `dcn20/dcn20_resource.h`, `dcn30/dcn30_resource.h`.
- Detected declarations: `enum dcn31_clk_src_array_id`, `function dcn31_dpp_destroy`, `function read_dce_straps`, `function dcn315_resource_destruct`, `function dcn31_dwbc_create`, `function dcn31_mmhubbub_create`, `function dcn315_destroy_resource_pool`, `function is_dual_plane`, `function source_format_to_bpp`, `function allow_pixel_rate_crb`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.