drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
Extension
.h
Size
11903 bytes
Lines
317
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn35_resource_pool {
	struct resource_pool base;
};

struct resource_pool *dcn35_create_resource_pool(
		const struct dc_init_data *init_data,
		struct dc *dc);

/* Defs for runtime init of registers */

#define OPP_REG_LIST_DCN20_RI(id) \
	OPP_REG_LIST_DCN10_RI(id), \
	OPP_DPG_REG_LIST_RI(id), \
	SRI_ARR(FMT_422_CONTROL, FMT, id), \
	SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)

#define OPP_REG_LIST_DCN35_RI(id) \
	OPP_REG_LIST_DCN20_RI(id), \
	SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)

#define VPG_DCN31_REG_LIST_RI(id) \
	SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
	SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
	SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \
	SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
	SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
	SRI_ARR(VPG_MEM_PWR, VPG, id)

#define AFMT_DCN31_REG_LIST_RI(id) \
	SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
	SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
	SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
	SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
	SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
	SRI_ARR(AFMT_60958_0, AFMT, id), \
	SRI_ARR(AFMT_60958_1, AFMT, id), \
	SRI_ARR(AFMT_60958_2, AFMT, id), \
	SRI_ARR(AFMT_MEM_PWR, AFMT, id)

/* Stream encoder */
#define SE_DCN35_REG_LIST_RI(id) \
	SRI_ARR(AFMT_CNTL, DIG, id), \
	SRI_ARR(DIG_FE_CNTL, DIG, id), \
	SRI_ARR(HDMI_CONTROL, DIG, id), \
	SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
	SRI_ARR(HDMI_GC, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
	SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \
	SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
	SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \
	SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
	SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\
	SRI_ARR(HDMI_ACR_32_0, DIG, id),\
	SRI_ARR(HDMI_ACR_32_1, DIG, id),\
	SRI_ARR(HDMI_ACR_44_0, DIG, id),\
	SRI_ARR(HDMI_ACR_44_1, DIG, id),\
	SRI_ARR(HDMI_ACR_48_0, DIG, id),\
	SRI_ARR(HDMI_ACR_48_1, DIG, id),\
	SRI_ARR(DP_DB_CNTL, DP, id), \
	SRI_ARR(DP_MSA_MISC, DP, id), \
	SRI_ARR(DP_MSA_VBID_MISC, DP, id), \
	SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
	SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
	SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
	SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
	SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
	SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \
	SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
	SRI_ARR(DP_PIXEL_FORMAT, DP, id), \
	SRI_ARR(DP_SEC_CNTL, DP, id), \
	SRI_ARR(DP_SEC_CNTL1, DP, id), \
	SRI_ARR(DP_SEC_CNTL2, DP, id), \
	SRI_ARR(DP_SEC_CNTL5, DP, id), \
	SRI_ARR(DP_SEC_CNTL6, DP, id), \
	SRI_ARR(DP_STEER_FIFO, DP, id), \
	SRI_ARR(DP_VID_M, DP, id), \
	SRI_ARR(DP_VID_N, DP, id), \
	SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
	SRI_ARR(DP_VID_TIMING, DP, id), \
	SRI_ARR(DP_SEC_AUD_N, DP, id), \

Annotation

Implementation Notes