drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

Extension

.h

Size

43650 bytes

Lines

673

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• core_types.h

Detected Declarations

• struct dcn42b_resource_pool

Annotated Snippet

struct dcn42b_resource_pool {
	struct resource_pool base;
};
struct resource_pool *dcn42b_create_resource_pool(
	const struct dc_init_data *init_data,
	struct dc *dc);

enum dc_status dcn42b_validate_bandwidth(struct dc *dc,
							  struct dc_state *context,
							  enum dc_validate_mode validate_mode);

void dcn42b_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

#endif /* _DCN42B_RESOURCE_H_ */

Annotation

• Immediate include surface: `core_types.h`.
• Detected declarations: `struct dcn42b_resource_pool`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.