drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
Extension: .c
Size: 13098 bytes
Lines: 308
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dcn401_soc_and_ip_translator.h
bounding_boxes/dcn4_soc_bb.h

Detected Declarations

function get_default_soc_bb
function dcn401_convert_dc_clock_table_to_soc_bb_clock_table
function dcn401_update_soc_bb_with_values_from_clk_mgr
function dcn401_update_soc_bb_with_values_from_vbios
function dcn401_update_soc_bb_with_values_from_software_policy
function apply_soc_bb_updates
function dcn401_get_soc_bb
function dcn401_get_ip_caps
function dcn401_construct_soc_and_ip_translator

Annotated Snippet

if (i < dml_clk_table->dcfclk.num_clk_values) {
				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz &&
						dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) {
					if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) {
						dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000;
						dml_clk_table->dcfclk.num_clk_values = (uint8_t)(i + 1);
					} else {
						dml_clk_table->dcfclk.clk_values_khz[i] = 0;
						dml_clk_table->dcfclk.num_clk_values = (uint8_t)i;
					}
				} else {
					dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
				}
			} else {
				dml_clk_table->dcfclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* fclk */
	if (dc_clk_table->num_entries_per_clk.num_fclk_levels) {
		dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_fclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->fclk.num_clk_values) {
				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz &&
						dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) {
					if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) {
						dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000;
						dml_clk_table->fclk.num_clk_values = (uint8_t)(i + 1);
					} else {
						dml_clk_table->fclk.clk_values_khz[i] = 0;
						dml_clk_table->fclk.num_clk_values = (uint8_t)i;
					}
				} else {
					dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000;
				}
			} else {
				dml_clk_table->fclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* uclk */
	if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
		dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->uclk.num_clk_values) {
				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz &&
						dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) {
					if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) {
						dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000;
						dml_clk_table->uclk.num_clk_values = (uint8_t)(i + 1);
					} else {
						dml_clk_table->uclk.clk_values_khz[i] = 0;
						dml_clk_table->uclk.num_clk_values = (uint8_t)i;
					}
				} else {
					dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
					#ifdef ENABLE_WCK
					dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio;
					#endif
				}
			} else {
				dml_clk_table->uclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* dispclk */
	if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
		dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->dispclk.num_clk_values) {
				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz &&
						dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) {
					if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) {
						dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000;
						dml_clk_table->dispclk.num_clk_values = (uint8_t)(i + 1);
					} else {
						dml_clk_table->dispclk.clk_values_khz[i] = 0;
						dml_clk_table->dispclk.num_clk_values = (uint8_t)i;
					}
				} else {
					dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
				}
			} else {
				dml_clk_table->dispclk.clk_values_khz[i] = 0;
			}
		}
	}

Annotation

Immediate include surface: `dcn401_soc_and_ip_translator.h`, `bounding_boxes/dcn4_soc_bb.h`.
Detected declarations: `function get_default_soc_bb`, `function dcn401_convert_dc_clock_table_to_soc_bb_clock_table`, `function dcn401_update_soc_bb_with_values_from_clk_mgr`, `function dcn401_update_soc_bb_with_values_from_vbios`, `function dcn401_update_soc_bb_with_values_from_software_policy`, `function apply_soc_bb_updates`, `function dcn401_get_soc_bb`, `function dcn401_get_ip_caps`, `function dcn401_construct_soc_and_ip_translator`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.