drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
Extension
.c
Size
8473 bytes
Lines
204
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (i < (int)dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
				int j, max_fclk = 0;

				dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
				for (j = 0; j < MAX_NUM_DPM_LVL; j++) {
					if ((uint32_t)(dc_clk_table->entries[j].fclk_mhz * 1000) > (uint32_t)max_fclk)
						max_fclk = dc_clk_table->entries[j].fclk_mhz * 1000;
					dml_clk_table->fclk.clk_values_khz[i] = max_fclk;
						if ((uint32_t)max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i])
						break;
				}
			} else {
				dml_clk_table->dcfclk.clk_values_khz[i] = 0;
				dml_clk_table->fclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* uclk */
	if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
		dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->uclk.num_clk_values) {
				dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
				dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio;
			} else {
				dml_clk_table->uclk.clk_values_khz[i] = 0;
				dml_clk_table->wck_ratio.clk_values_khz[i] = 0;
			}
		}
	}

	/* dispclk */
	if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
		dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->dispclk.num_clk_values) {
				dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
			} else {
				dml_clk_table->dispclk.clk_values_khz[i] = 0;
			}
		}
		vmin_limit->dispclk_khz = min(dc_clk_table->entries[0].dispclk_mhz * 1000, vmin_limit->dispclk_khz);
		/* dispclk is always fine-grain */
		dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels >= 2 ? 2 : 1;
		dml_clk_table->dispclk.clk_values_khz[0] = 0;
		dml_clk_table->dispclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dispclk_levels - 1].dispclk_mhz * 1000;
	}

	/* dppclk */
	if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
		dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->dppclk.num_clk_values) {
				dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
			} else {
				dml_clk_table->dppclk.clk_values_khz[i] = 0;
			}
		}
		/* dppclk is always fine-grain */
		dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels >= 2 ? 2 : 1;
		dml_clk_table->dppclk.clk_values_khz[0] = 0;
		dml_clk_table->dppclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dppclk_levels - 1].dppclk_mhz * 1000;
	}

	/* dtbclk */
	if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
		dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->dtbclk.num_clk_values) {
				dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
			} else {
				dml_clk_table->dtbclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* socclk */
	if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
		dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels;
		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
			if (i < dml_clk_table->socclk.num_clk_values) {
				dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
			} else {
				dml_clk_table->socclk.clk_values_khz[i] = 0;
			}
		}
	}

	/* dram config */

Annotation

Implementation Notes