drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c- Extension
.c- Size
- 17597 bytes
- Lines
- 568
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
../dmub_srv.hdmub_reg.hdmub_dcn32.hdc/dc_types.hdc_hw_types.hdcn/dcn_3_2_0_offset.hdcn/dcn_3_2_0_sh_mask.h
Detected Declarations
function filesfunction dmub_dcn32_get_fb_base_offsetfunction dmub_dcn32_translate_addrfunction dmub_dcn32_resetfunction dmub_dcn32_reset_releasefunction dmub_dcn32_backdoor_loadfunction dmub_dcn32_backdoor_load_zfb_modefunction dmub_dcn32_setup_windowsfunction dmub_dcn32_setup_mailboxfunction dmub_dcn32_get_inbox1_wptrfunction dmub_dcn32_get_inbox1_rptrfunction dmub_dcn32_set_inbox1_wptrfunction dmub_dcn32_setup_out_mailboxfunction dmub_dcn32_get_outbox1_wptrfunction dmub_dcn32_set_outbox1_rptrfunction dmub_dcn32_is_hw_initfunction dmub_dcn32_is_supportedfunction dmub_dcn32_set_gpintfunction dmub_dcn32_is_gpint_ackedfunction dmub_dcn32_get_gpint_responsefunction dmub_dcn32_get_gpint_dataoutfunction dmub_dcn32_get_fw_boot_statusfunction dmub_dcn32_enable_dmub_boot_optionsfunction dmub_dcn32_skip_dmub_panel_power_sequencefunction dmub_dcn32_setup_outbox0function dmub_dcn32_get_outbox0_wptrfunction dmub_dcn32_set_outbox0_rptrfunction dmub_dcn32_get_current_timefunction dmub_dcn32_get_diagnostic_datafunction dmub_dcn32_configure_dmub_in_system_memoryfunction dmub_dcn32_send_inbox0_cmdfunction dmub_dcn32_clear_inbox0_ack_registerfunction dmub_dcn32_read_inbox0_ack_registerfunction dmub_dcn32_save_surf_addr
Annotated Snippet
if (index) {
REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
} else {
REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part);
REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
}
REG_WRITE(DMCUB_SCRATCH15, !index);
} else if (subvp_index == 1) {
index = REG_READ(DMCUB_SCRATCH23);
if (index) {
REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
} else {
REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part);
REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
}
REG_WRITE(DMCUB_SCRATCH23, !index);
} else {
return;
}
}
Annotation
- Immediate include surface: `../dmub_srv.h`, `dmub_reg.h`, `dmub_dcn32.h`, `dc/dc_types.h`, `dc_hw_types.h`, `dcn/dcn_3_2_0_offset.h`, `dcn/dcn_3_2_0_sh_mask.h`.
- Detected declarations: `function files`, `function dmub_dcn32_get_fb_base_offset`, `function dmub_dcn32_translate_addr`, `function dmub_dcn32_reset`, `function dmub_dcn32_reset_release`, `function dmub_dcn32_backdoor_load`, `function dmub_dcn32_backdoor_load_zfb_mode`, `function dmub_dcn32_setup_windows`, `function dmub_dcn32_setup_mailbox`, `function dmub_dcn32_get_inbox1_wptr`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.