drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
Extension
.c
Size
23551 bytes
Lines
760
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (payload_size_bytes <= msg_index * 4) {
			break;
		}

		switch (msg_index) {
		case 0:
			REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
			break;
		case 1:
			REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
			break;
		case 2:
			REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
			break;
		case 3:
			REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
			break;
		case 4:
			REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
			break;
		case 5:
			REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
			break;
		case 6:
			REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
			break;
		case 7:
			REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
			break;
		case 8:
			REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
			break;
		case 9:
			REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
			break;
		case 10:
			REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
			break;
		case 11:
			REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
			break;
		case 12:
			REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
			break;
		case 13:
			REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
			break;
		case 14:
			REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
			break;
		}
	}

	/* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
	 * interrupt.
	 */
	REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
}

uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)
{
	uint32_t status;

	REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
	return status;
}

void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
		union dmub_rb_cmd *cmd)
{
	uint32_t *dwords = (uint32_t *)cmd;

	static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");

	dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);
	dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);
	dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);
	dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);
	dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);
	dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);
	dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);
	dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);
	dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);
	dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);
	dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);
	dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);
	dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);
	dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);
	dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);
	dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);

Annotation

Implementation Notes