drivers/gpu/drm/amd/display/include/bios_parser_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/include/bios_parser_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/include/bios_parser_types.h
Extension
.h
Size
10844 bytes
Lines
364
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bp_encoder_control {
	enum bp_encoder_control_action action;
	enum engine_id engine_id;
	enum transmitter transmitter;
	enum signal_type signal;
	enum dc_lane_count lanes_number;
	enum dc_color_depth color_depth;
	bool enable_dp_audio;
	uint32_t pixel_clock; /* khz */
};

struct bp_external_encoder_control {
	enum bp_external_encoder_control_action action;
	enum engine_id engine_id;
	enum dc_link_rate link_rate;
	enum dc_lane_count lanes_number;
	enum signal_type signal;
	enum dc_color_depth color_depth;
	bool coherent;
	struct graphics_object_id encoder_id;
	struct graphics_object_id connector_obj_id;
	uint32_t pixel_clock; /* in KHz */
};

struct bp_crtc_source_select {
	enum engine_id engine_id;
	enum controller_id controller_id;
	enum signal_type sink_signal;
	enum dc_color_depth color_depth;
};

struct bp_transmitter_control {
	enum bp_transmitter_control_action action;
	enum engine_id engine_id;
	enum transmitter transmitter; /* PhyId */
	enum dc_lane_count lanes_number;
	enum clock_source_id pll_id; /* needed for DCE 4.0 */
	enum signal_type signal;
	enum dc_color_depth color_depth; /* not used for DCE6.0 */
	enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
	enum tx_ffe_id txffe_sel; /* used for DCN3 */
	enum engine_id hpo_engine_id; /* used for DCN3 */
	struct graphics_object_id connector_obj_id;
	/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
	 * be pixel clock * deep_color_ratio (in KHz)
	 */
	uint32_t pixel_clock;
	uint32_t lane_select;
	uint32_t lane_settings;
	bool coherent;
	bool multi_path;
	bool single_pll_mode;
};

struct bp_load_detection_parameters {
	enum engine_id engine_id;
	uint16_t device_id;
};

struct bp_hw_crtc_timing_parameters {
	enum controller_id controller_id;
	/* horizontal part */
	uint32_t h_total;
	uint32_t h_addressable;
	uint32_t h_overscan_left;
	uint32_t h_overscan_right;
	uint32_t h_sync_start;
	uint32_t h_sync_width;

	/* vertical part */
	uint32_t v_total;
	uint32_t v_addressable;
	uint32_t v_overscan_top;
	uint32_t v_overscan_bottom;
	uint32_t v_sync_start;
	uint32_t v_sync_width;

	struct timing_flags {
		uint32_t INTERLACE:1;
		uint32_t PIXEL_REPETITION:4;
		uint32_t HSYNC_POSITIVE_POLARITY:1;
		uint32_t VSYNC_POSITIVE_POLARITY:1;
		uint32_t HORZ_COUNT_BY_TWO:1;
	} flags;
};

struct bp_adjust_pixel_clock_parameters {
	/* Input: Signal Type - to be converted to Encoder mode */
	enum signal_type signal_type;
	/* Input: Encoder object id */

Annotation

Implementation Notes