drivers/gpu/drm/amd/display/include/ddc_service_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/include/ddc_service_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/include/ddc_service_types.h
Extension
.h
Size
4893 bytes
Lines
136
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct display_sink_capability {
	/* dongle type (DP converter, CV smart dongle) */
	enum display_dongle_type dongle_type;
	bool is_dongle_type_one;

	/**********************************************************
	 capabilities going INTO SINK DEVICE (stream capabilities)
	 **********************************************************/
	/* Dongle's downstream count. */
	uint32_t downstrm_sink_count;
	/* Is dongle's downstream count info field (downstrm_sink_count)
	 * valid. */
	bool downstrm_sink_count_valid;

	/* Maximum additional audio delay in microsecond (us) */
	uint32_t additional_audio_delay;
	/* Audio latency value in microsecond (us) */
	uint32_t audio_latency;
	/* Interlace video latency value in microsecond (us) */
	uint32_t video_latency_interlace;
	/* Progressive video latency value in microsecond (us) */
	uint32_t video_latency_progressive;
	/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
	uint32_t max_hdmi_pixel_clock;
	/* Dongle caps: Maximum deep color supported over dongle for HDMI */
	enum dc_color_depth max_hdmi_deep_color;

	/************************************************************
	 capabilities going OUT OF SOURCE DEVICE (link capabilities)
	 ************************************************************/
	/* support for Spread Spectrum(SS) */
	bool ss_supported;
	/* DP link settings (laneCount, linkRate, Spread) */
	uint32_t dp_link_lane_count;
	uint32_t dp_link_rate;
	uint32_t dp_link_spead;

	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
	bool is_dp_hdmi_s3d_converter;
	/* to check if we have queried the display capability
	 * for eDP panel already. */
	bool is_edp_sink_cap_valid;

	enum ddc_transaction_type transaction_type;
	enum signal_type signal;
};

struct av_sync_data {
	uint8_t av_granularity;/* DPCD 00023h */
	uint8_t aud_dec_lat1;/* DPCD 00024h */
	uint8_t aud_dec_lat2;/* DPCD 00025h */
	uint8_t aud_pp_lat1;/* DPCD 00026h */
	uint8_t aud_pp_lat2;/* DPCD 00027h */
	uint8_t vid_inter_lat;/* DPCD 00028h */
	uint8_t vid_prog_lat;/* DPCD 00029h */
	uint8_t aud_del_ins1;/* DPCD 0002Bh */
	uint8_t aud_del_ins2;/* DPCD 0002Ch */
	uint8_t aud_del_ins3;/* DPCD 0002Dh */
};

#endif /* __DAL_DDC_SERVICE_TYPES_H__ */

Annotation

Implementation Notes