drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h- Extension
.h- Size
- 19243 bytes
- Lines
- 535
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct ta_dtm_topology_update_input_v2struct ta_dtm_topology_update_input_v3struct ta_dtm_topology_assr_enablestruct ta_dtm_shared_memorystruct ta_hdcp_cmd_hdcp1_create_session_inputstruct ta_hdcp_cmd_hdcp1_create_session_outputstruct ta_hdcp_cmd_hdcp1_destroy_session_inputstruct ta_hdcp_cmd_hdcp1_first_part_authentication_inputstruct ta_hdcp_cmd_hdcp1_first_part_authentication_outputstruct ta_hdcp_cmd_hdcp1_second_part_authentication_inputstruct ta_hdcp_cmd_hdcp1_second_part_authentication_outputstruct ta_hdcp_cmd_hdcp1_enable_encryption_inputstruct ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_inputstruct ta_hdcp_cmd_hdcp1_get_encryption_status_inputstruct ta_hdcp_cmd_hdcp1_get_encryption_status_outputstruct ta_hdcp_cmd_hdcp2_create_session_input_v2struct ta_hdcp_cmd_hdcp2_create_session_output_v2struct ta_hdcp_cmd_hdcp2_destroy_session_inputstruct ta_hdcp_cmd_hdcp2_authentication_message_v2struct ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2struct ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2struct ta_hdcp_cmd_hdcp2_set_encryption_inputstruct ta_hdcp_cmd_hdcp2_get_encryption_status_inputstruct ta_hdcp_cmd_hdcp2_get_encryption_status_outputstruct ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_inputstruct ta_hdcp_cmd_set_srm_inputstruct ta_hdcp_cmd_set_srm_outputstruct ta_hdcp_cmd_get_srm_outputstruct ta_hdcp_shared_memoryenum bgd_security_hdcp_encryption_levelenum bgd_security_hdcp2_content_typeenum ta_dtm_commandenum ta_dtm_statusenum ta_dtm_hdcp_version_max_supportedenum ta_dtm_encoder_typeenum ta_hdcp_commandenum ta_hdcp2_msg_idenum ta_hdcp2_hdcp2_msg_id_max_sizeenum ta_hdcp_statusenum ta_hdcp_authentication_statusenum ta_hdcp2_msg_authentication_statusenum ta_hdcp_content_typeenum ta_hdcp_content_type_negotiation_typeenum ta_hdcp2_version
Annotated Snippet
struct ta_dtm_topology_update_input_v2 {
/* display handle is unique across the driver and is used to identify a display */
/* for all security interfaces which reference displays such as HDCP */
uint32_t display_handle;
uint32_t is_active;
uint32_t is_miracast;
uint32_t controller;
uint32_t ddc_line;
uint32_t dig_be;
uint32_t dig_fe;
uint32_t dp_mst_vcid;
uint32_t is_assr;
/*uint32_t is_frl;*/ /*todo*/
uint32_t max_hdcp_supported_version;
};
/* For security reason/HW may change value, these encoder type enum values are not HW register values */
/* Security code will check real HW register values and these SW enum values */
enum ta_dtm_encoder_type {
TA_DTM_ENCODER_TYPE__INVALID = 0,
TA_DTM_ENCODER_TYPE__FRL = 0x20,
TA_DTM_ENCODER_TYPE__DIG = 0x10
};
/* @enum ta_dtm_dio_output_type
* This enum defines software value for dio_output_type
*/
typedef enum {
TA_DTM_DIO_OUTPUT_TYPE__INVALID,
TA_DTM_DIO_OUTPUT_TYPE__DIRECT,
TA_DTM_DIO_OUTPUT_TYPE__DPIA
} ta_dtm_dio_output_type;
struct ta_dtm_topology_update_input_v3 {
/* display handle is unique across the driver and is used to identify a display */
/* for all security interfaces which reference displays such as HDCP */
/* link_hdcp_cap means link is HDCP-capable for audio HDCP capable property(informational), not for other logic(e.g. Crossbar) */
uint32_t display_handle;
uint32_t is_active;
uint32_t is_miracast;
uint32_t controller;
uint32_t ddc_line;
uint32_t link_enc;
uint32_t stream_enc;
uint32_t dp_mst_vcid;
uint32_t is_assr;
uint32_t max_hdcp_supported_version;
enum ta_dtm_encoder_type encoder_type;
uint32_t phy_id;
uint32_t link_hdcp_cap;
ta_dtm_dio_output_type dio_output_type;
uint32_t dio_output_id;
};
struct ta_dtm_topology_assr_enable {
uint32_t display_topology_dig_be_index;
};
/**
* Output structures
*/
/* No output structures yet */
union ta_dtm_cmd_input {
struct ta_dtm_topology_update_input_v2 topology_update_v2;
struct ta_dtm_topology_assr_enable topology_assr_enable;
struct ta_dtm_topology_update_input_v3 topology_update_v3;
};
union ta_dtm_cmd_output {
uint32_t reserved;
};
struct ta_dtm_shared_memory {
uint32_t cmd_id;
uint32_t resp_id;
enum ta_dtm_status dtm_status;
uint32_t reserved;
union ta_dtm_cmd_input dtm_in_message;
union ta_dtm_cmd_output dtm_out_message;
};
int psp_cmd_submit_buf(struct psp_context *psp, struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd,
uint64_t fence_mc_addr);
enum { PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE = 5120 };
enum ta_hdcp_command {
TA_HDCP_COMMAND__INITIALIZE,
Annotation
- Detected declarations: `struct ta_dtm_topology_update_input_v2`, `struct ta_dtm_topology_update_input_v3`, `struct ta_dtm_topology_assr_enable`, `struct ta_dtm_shared_memory`, `struct ta_hdcp_cmd_hdcp1_create_session_input`, `struct ta_hdcp_cmd_hdcp1_create_session_output`, `struct ta_hdcp_cmd_hdcp1_destroy_session_input`, `struct ta_hdcp_cmd_hdcp1_first_part_authentication_input`, `struct ta_hdcp_cmd_hdcp1_first_part_authentication_output`, `struct ta_hdcp_cmd_hdcp1_second_part_authentication_input`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.