drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c- Extension
.c- Size
- 23370 bytes
- Lines
- 709
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
mod_info_packet.hcore_types.hdc_types.hmod_shared.hmod_freesync.hdc.h
Detected Declarations
enum vsc_packet_revisionenum ColorimetryRGBDPenum ColorimetryYCCDPfunction set_vsc_packet_colorimetry_datafunction mod_build_vsc_infopacketfunction registerfunction mod_build_hf_vsif_infopacketfunction mod_build_adaptive_sync_infopacketfunction mod_build_adaptive_sync_infopacket_v1function mod_build_adaptive_sync_infopacket_v2
Annotated Snippet
switch (stream->timing.timing_3d_format) {
case TIMING_3D_FORMAT_HW_FRAME_PACKING:
case TIMING_3D_FORMAT_SW_FRAME_PACKING:
case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
case TIMING_3D_FORMAT_TB_SW_PACKED:
info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom.
break;
case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA:
case TIMING_3D_FORMAT_INBAND_FA:
info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1
break;
case TIMING_3D_FORMAT_SIDE_BY_SIDE:
case TIMING_3D_FORMAT_SBS_SW_PACKED:
info_packet->sb[0] = 0x04; // Side-by-side
break;
default:
info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0.
break;
}
}
/* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication.
* Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry
* format to the DP Sink device with VSC SDP only when the DP Sink device supports it
* (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST
* register (DPCD Address 02210h, bit 3) is set to 1).
* (Requires VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit set to 1 in DPCD 02210h. This
* DPCD register is exposed in the new Extended Receiver Capability field for DPCD Rev. 1.4
* (and higher). When MISC1. bit 6. is Set to 1, a Source device uses a VSC SDP to indicate
* the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and
* MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").)
*/
if (vsc_packet_revision == vsc_packet_rev5) {
/* Secondary-data Packet ID = 0 */
info_packet->hb0 = 0x00;
/* 07h - Packet Type Value indicating Video Stream Configuration packet */
info_packet->hb1 = 0x07;
/* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication. */
info_packet->hb2 = 0x05;
/* 13h = VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/Colorimetry Format indication (HB2 = 05h). */
info_packet->hb3 = 0x13;
info_packet->valid = true;
set_vsc_packet_colorimetry_data(stream, info_packet, cs, tf);
}
if (vsc_packet_revision == vsc_packet_rev7) {
/* Secondary-data Packet ID = 0 */
info_packet->hb0 = 0x00;
/* 07h - Packet Type Value indicating Video Stream Configuration packet */
info_packet->hb1 = 0x07;
/* 07h = VSC SDP supporting 3D stereo, PR, and Pixel Encoding/Colorimetry Format indication. */
info_packet->hb2 = 0x07;
/* 13h = VSC SDP supporting 3D stereo, + PR, + Pixel Encoding/Colorimetry Format indication (HB2 = 07h). */
info_packet->hb3 = 0x13;
info_packet->valid = true;
set_vsc_packet_colorimetry_data(stream, info_packet, cs, tf);
}
}
/**
* mod_build_hf_vsif_infopacket - Prepare HDMI Vendor Specific info frame.
* Follows HDMI Spec to build up Vendor Specific info frame
*
* @stream: contains data we may need to construct VSIF (i.e. timing_3d_format, etc.)
* @info_packet: output structure where to store VSIF
* @ALLMEnabled: indicates whether ALLM HF-VSIF should be generated
* @ALLMValue: ALLM bit value to advertise in HF-VSIF
*/
void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue)
{
unsigned int length = 5;
bool hdmi_vic_mode = false;
uint8_t checksum = 0;
uint32_t i = 0;
enum dc_timing_3d_format format;
bool bALLM = (bool)ALLMEnabled;
bool bALLMVal = (bool)ALLMValue;
int CCBPC = 0;
info_packet->valid = false;
format = stream->timing.timing_3d_format;
if (stream->view_format == VIEW_3D_FORMAT_NONE)
format = TIMING_3D_FORMAT_NONE;
Annotation
- Immediate include surface: `mod_info_packet.h`, `core_types.h`, `dc_types.h`, `mod_shared.h`, `mod_freesync.h`, `dc.h`.
- Detected declarations: `enum vsc_packet_revision`, `enum ColorimetryRGBDP`, `enum ColorimetryYCCDP`, `function set_vsc_packet_colorimetry_data`, `function mod_build_vsc_infopacket`, `function register`, `function mod_build_hf_vsif_infopacket`, `function mod_build_adaptive_sync_infopacket`, `function mod_build_adaptive_sync_infopacket_v1`, `function mod_build_adaptive_sync_infopacket_v2`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.