drivers/gpu/drm/amd/include/amd_pcie.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/amd_pcie.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/amd_pcie.h
Extension
.h
Size
4277 bytes
Lines
87
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __AMD_PCIE_H__
#define __AMD_PCIE_H__

/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4        0x00080000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5        0x00100000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16

/* Following flags shows PCIe link speed supported by ASIC H/W.*/
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4   0x00000008
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5   0x00000010
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0

/* gen: chipset 1/2, asic 1/2/3 */
#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
				      | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)

/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */

#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1          0x00000001
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2          0x00000002
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4          0x00000004
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8          0x00000008
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12         0x00000010
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16         0x00000020
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32         0x00000040
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_MASK        0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_SHIFT       0

#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_MASK        0xFFFF0000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16

/* 1/2/4/8/16 lanes */
#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)

#define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \
					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 \
					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 \
					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 \
					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)

#endif

Annotation

Implementation Notes