drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_sh_mask.h- Extension
.h- Size
- 192894 bytes
- Lines
- 1808
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _athub_1_8_0_SH_MASK_HEADER
#define _athub_1_8_0_SH_MASK_HEADER
// addressBlock: aid_athub_atsdec
//ATC_ATS_CNTL
#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000F0000L
#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
//ATC_ATS_CNTL2
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR__SHIFT 0x0
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR__SHIFT 0x8
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV__SHIFT 0x10
#define ATC_ATS_CNTL2__TRANSLATION_STALL__SHIFT 0x18
#define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE__SHIFT 0x19
#define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE__SHIFT 0x1a
#define ATC_ATS_CNTL2__RESERVED__SHIFT 0x1b
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR_MASK 0x000000FFL
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR_MASK 0x0000FF00L
#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV_MASK 0x00FF0000L
#define ATC_ATS_CNTL2__TRANSLATION_STALL_MASK 0x01000000L
#define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE_MASK 0x02000000L
#define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE_MASK 0x04000000L
#define ATC_ATS_CNTL2__RESERVED_MASK 0xF8000000L
//ATC_ATS_CNTL3
#define ATC_ATS_CNTL3__RESERVED__SHIFT 0x0
#define ATC_ATS_CNTL3__RESERVED_MASK 0xFFFFFFFFL
//ATC_ATS_CNTL4
#define ATC_ATS_CNTL4__RESERVED__SHIFT 0x0
#define ATC_ATS_CNTL4__RESERVED_MASK 0xFFFFFFFFL
//ATC_ATS_MISC_CNTL
#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST__SHIFT 0x10
#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST__SHIFT 0x11
#define ATC_ATS_MISC_CNTL__DEBUG_COLLISION__SHIFT 0x12
#define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE__SHIFT 0x13
#define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL__SHIFT 0x1d
#define ATC_ATS_MISC_CNTL__RESERVED__SHIFT 0x1e
#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST_MASK 0x00010000L
#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST_MASK 0x00020000L
#define ATC_ATS_MISC_CNTL__DEBUG_COLLISION_MASK 0x00040000L
#define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE_MASK 0x1FF80000L
#define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL_MASK 0x20000000L
#define ATC_ATS_MISC_CNTL__RESERVED_MASK 0xC0000000L
//ATC_ATS_STATUS
#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
#define ATC_ATS_STATUS__FED_IND__SHIFT 0x3
#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
#define ATC_ATS_STATUS__FED_IND_MASK 0x00000008L
//ATC_PERFCOUNTER0_CFG
#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//ATC_PERFCOUNTER1_CFG
#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//ATC_PERFCOUNTER2_CFG
#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFLAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.