drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_offset.h- Extension
.h- Size
- 53615 bytes
- Lines
- 524
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _athub_2_1_0_OFFSET_HEADER
#define _athub_2_1_0_OFFSET_HEADER
// addressBlock: athub_atsdec
// base address: 0x3000
#define mmATHUB_ATS_MODE_CNTL 0x0000
#define mmATHUB_ATS_MODE_CNTL_BASE_IDX 0
#define mmATHUB_SHARED_VIRT_RESET_REQ 0x0001
#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x0002
#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define mmATC_ATS_CNTL 0x0003
#define mmATC_ATS_CNTL_BASE_IDX 0
#define mmATC_ATS_FAULT_CNTL 0x0006
#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
#define mmATHUB_MISC_CNTL 0x0009
#define mmATHUB_MISC_CNTL_BASE_IDX 0
#define mmATHUB_MEM_POWER_LS 0x000a
#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
#define mmATC_ATS_SDPPORT_CNTL 0x000b
#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
#define mmATC_ATS_CNTL2 0x000d
#define mmATC_ATS_CNTL2_BASE_IDX 0
#define mmATC_ATS_TR_QOS_CNTL 0x000e
#define mmATC_ATS_TR_QOS_CNTL_BASE_IDX 0
#define mmATC_ATS_MISC_CNTL 0x000f
#define mmATC_ATS_MISC_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER0_CFG 0x0010
#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER1_CFG 0x0011
#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER2_CFG 0x0012
#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER3_CFG 0x0013
#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0014
#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER_LO 0x0015
#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
#define mmATC_PERFCOUNTER_HI 0x0016
#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
#define mmATS_IH_CREDIT 0x0017
#define mmATS_IH_CREDIT_BASE_IDX 0
#define mmATHUB_IH_CREDIT 0x0018
#define mmATHUB_IH_CREDIT_BASE_IDX 0
#define mmATC_ATS_GFX_ATCL2_STATUS 0x0019
#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x001a
#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO 0x001b
#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_ADDR 0x001c
#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO2 0x001d
#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL 0x001e
#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PASID_CNTL 0x001f
#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0020
#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0021
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
#define mmATHUB_COMMAND 0x0022
#define mmATHUB_COMMAND_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x0023
#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x0024
#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x0025
#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x0026
#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x0027
#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x0028
#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0029
#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x002a
#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x002b
#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x002cAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.