drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_sh_mask.h- Extension
.h- Size
- 254625 bytes
- Lines
- 2379
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _athub_2_1_0_SH_MASK_HEADER
#define _athub_2_1_0_SH_MASK_HEADER
// addressBlock: athub_atsdec
//ATHUB_ATS_MODE_CNTL
#define ATHUB_ATS_MODE_CNTL__HOST_TRANS_ENABLE__SHIFT 0x0
#define ATHUB_ATS_MODE_CNTL__CONSOLE_IOV_ENABLE__SHIFT 0x1
#define ATHUB_ATS_MODE_CNTL__HOST_TRANS_ENABLE_MASK 0x00000001L
#define ATHUB_ATS_MODE_CNTL__CONSOLE_IOV_ENABLE_MASK 0x00000002L
//ATHUB_SHARED_VIRT_RESET_REQ
#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
//ATHUB_SHARED_ACTIVE_FCN_ID
#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
//ATC_ATS_CNTL
#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
#define ATC_ATS_CNTL__GUEST_TRANS_MISS_MODE__SHIFT 0x18
#define ATC_ATS_CNTL__KEEP_VMID_BUSY_BY_INTR__SHIFT 0x19
#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L
#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L
#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
#define ATC_ATS_CNTL__GUEST_TRANS_MISS_MODE_MASK 0x01000000L
#define ATC_ATS_CNTL__KEEP_VMID_BUSY_BY_INTR_MASK 0x02000000L
//ATC_ATS_FAULT_CNTL
#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
//ATC_ATS_DEFAULT_PAGE_LOW
#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
//ATC_TRANS_FAULT_RSPCNTRL
#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10
#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11
#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12
#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13
#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14
#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15
#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16
#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17
#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18
#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19
#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a
#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b
#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c
#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d
#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e
#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f
#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.