drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h- Extension
.h- Size
- 25632 bytes
- Lines
- 260
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _athub_3_0_0_OFFSET_HEADER
#define _athub_3_0_0_OFFSET_HEADER
// addressBlock: athub_xpbdec
// base address: 0x3000
#define regXPB_RTR_SRC_APRTR0 0x0000
#define regXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR1 0x0001
#define regXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR2 0x0002
#define regXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR3 0x0003
#define regXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR4 0x0004
#define regXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR5 0x0005
#define regXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR6 0x0006
#define regXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR7 0x0007
#define regXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR8 0x0008
#define regXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR9 0x0009
#define regXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR10 0x000a
#define regXPB_RTR_SRC_APRTR10_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR11 0x000b
#define regXPB_RTR_SRC_APRTR11_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR12 0x000c
#define regXPB_RTR_SRC_APRTR12_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR13 0x000d
#define regXPB_RTR_SRC_APRTR13_BASE_IDX 0
#define regXPB_RTR_DEST_MAP0 0x000e
#define regXPB_RTR_DEST_MAP0_BASE_IDX 0
#define regXPB_RTR_DEST_MAP1 0x000f
#define regXPB_RTR_DEST_MAP1_BASE_IDX 0
#define regXPB_RTR_DEST_MAP2 0x0010
#define regXPB_RTR_DEST_MAP2_BASE_IDX 0
#define regXPB_RTR_DEST_MAP3 0x0011
#define regXPB_RTR_DEST_MAP3_BASE_IDX 0
#define regXPB_RTR_DEST_MAP4 0x0012
#define regXPB_RTR_DEST_MAP4_BASE_IDX 0
#define regXPB_RTR_DEST_MAP5 0x0013
#define regXPB_RTR_DEST_MAP5_BASE_IDX 0
#define regXPB_RTR_DEST_MAP6 0x0014
#define regXPB_RTR_DEST_MAP6_BASE_IDX 0
#define regXPB_RTR_DEST_MAP7 0x0015
#define regXPB_RTR_DEST_MAP7_BASE_IDX 0
#define regXPB_RTR_DEST_MAP8 0x0016
#define regXPB_RTR_DEST_MAP8_BASE_IDX 0
#define regXPB_RTR_DEST_MAP9 0x0017
#define regXPB_RTR_DEST_MAP9_BASE_IDX 0
#define regXPB_RTR_DEST_MAP10 0x0018
#define regXPB_RTR_DEST_MAP10_BASE_IDX 0
#define regXPB_RTR_DEST_MAP11 0x0019
#define regXPB_RTR_DEST_MAP11_BASE_IDX 0
#define regXPB_RTR_DEST_MAP12 0x001a
#define regXPB_RTR_DEST_MAP12_BASE_IDX 0
#define regXPB_RTR_DEST_MAP13 0x001b
#define regXPB_RTR_DEST_MAP13_BASE_IDX 0
#define regXPB_CLG_CFG0 0x001c
#define regXPB_CLG_CFG0_BASE_IDX 0
#define regXPB_CLG_CFG1 0x001d
#define regXPB_CLG_CFG1_BASE_IDX 0
#define regXPB_CLG_CFG2 0x001e
#define regXPB_CLG_CFG2_BASE_IDX 0
#define regXPB_CLG_CFG3 0x001f
#define regXPB_CLG_CFG3_BASE_IDX 0
#define regXPB_CLG_CFG4 0x0020
#define regXPB_CLG_CFG4_BASE_IDX 0
#define regXPB_CLG_CFG5 0x0021
#define regXPB_CLG_CFG5_BASE_IDX 0
#define regXPB_CLG_CFG6 0x0022
#define regXPB_CLG_CFG6_BASE_IDX 0
#define regXPB_CLG_CFG7 0x0023
#define regXPB_CLG_CFG7_BASE_IDX 0
#define regXPB_CLG_EXTRA 0x0024
#define regXPB_CLG_EXTRA_BASE_IDX 0
#define regXPB_CLG_EXTRA_MSK 0x0025
#define regXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define regXPB_LB_ADDR 0x0026
#define regXPB_LB_ADDR_BASE_IDX 0
#define regXPB_WCB_STS 0x0027
#define regXPB_WCB_STS_BASE_IDX 0
#define regXPB_HST_CFG 0x0028
#define regXPB_HST_CFG_BASE_IDX 0
#define regXPB_P2P_BAR_CFG 0x0029Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.